Add bitwise $bweqx and $bwmux cells
The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`) cells enable compact encoding and decoding of 3-valued logic signals using multiple 2-valued signals.
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@@ -31,6 +31,7 @@ extern void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell);
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extern void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell);
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extern void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell);
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extern void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell);
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extern void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell);
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extern void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell);
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extern void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell);
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extern void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell);
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