github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-05 15:45:07 +00:00
Code Issues Releases Wiki Activity

rtlil: represent Const strings as std::string

Browse Source
This commit is contained in:
Emil J. Tywoniak
2024-10-09 19:39:45 +02:00
parent 61ed9b6263
commit 785bd44da7
90 changed files with 947 additions and 643 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
techlibs/xilinx/xilinx_dffopt.cc
View File

@@ -79,7 +79,7 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool
for (int j = 0; j < GetSize(select.second); j++)
if (i & 1 << idx_sel[j])
sel_lut_idx |= 1 << j;
bool select_val = (select.first.bits[sel_lut_idx] == State::S1);
bool select_val = (select.first[sel_lut_idx] == State::S1);
bool new_bit;
if (select_val ^ select_inv) {
// Use alt_data.
@@ -90,9 +90,9 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool
} else {
// Use original LUT.
int lut_idx = i >> idx_data & ((1 << GetSize(data.second)) - 1);
new_bit = data.first.bits[lut_idx] == State::S1;
new_bit = data.first[lut_idx] == State::S1;
}
result.first.bits[i] = new_bit ? State::S1 : State::S0;
result.first.bits()[i] = new_bit ? State::S1 : State::S0;
}
return true;
}
@@ -212,7 +212,7 @@ lut_sigin_done:
if (cell->hasParam(ID(IS_D_INVERTED)) && cell->getParam(ID(IS_D_INVERTED)).as_bool()) {
// Flip all bits in the LUT.
for (int i = 0; i < GetSize(lut_d.first); i++)
lut_d.first.bits[i] = (lut_d.first.bits[i] == State::S1) ? State::S0 : State::S1;
lut_d.first.bits()[i] = (lut_d.first[i] == State::S1) ? State::S0 : State::S1;
}
LutData lut_d_post_ce;