fix whitespace issues

2026-04-24 19:40:49 +00:00 · 2025-08-06 15:32:36 -04:00
parent fe59b6d3db
commit 7e0157ba2b
2 changed files with 8 additions and 8 deletions
--- a/tests/verilog/package_import_separate.sv
+++ b/tests/verilog/package_import_separate.sv
@@ -2,7 +2,7 @@ package config_pkg;
  localparam integer
    DATA_WIDTH = 8,
    ADDR_WIDTH = 4;
-    
+
  localparam logic [2:0]
    IDLE = 3'b000,
    START = 3'b001,
@@ -10,4 +10,4 @@ package config_pkg;
    ODD_PARITY = 3'b011,
    STOP = 3'b100,
    DONE = 3'b101;
-endpackage 
+endpackage