proc_dff: narrow $priority
This commit is contained in:
Emil J. Tywoniak
parent
d027b62d1c
commit
8192cee0b3
@ -177,44 +177,46 @@ void gen_dffsr(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
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struct Builder {
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using BitControl = std::pair<std::optional<SigBit>, std::optional<SigBit>>;
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std::vector<RTLIL::Cell*> cells {};
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std::unordered_map<std::vector<BitRule>, BitControl> map = {};
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using MaybeBitControl = std::pair<std::optional<SigBit>, std::optional<SigBit>>;
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std::unordered_map<std::vector<BitRule>, MaybeBitControl> map = {};
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RTLIL::Module* mod;
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RTLIL::Wire* prioritized;
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RTLIL::SigSpec priority_in;
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std::vector<RTLIL::State> priority_pol;
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RTLIL::Process* proc;
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bool set_pol, reset_pol;
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Builder(RTLIL::Module* mod, size_t rule_count, bool s, bool r) : mod(mod), set_pol(s), reset_pol(r) {
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prioritized = mod->addWire(NEW_ID, 0);
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RTLIL::Cell* priority = mod->addPriority(NEW_ID, SigSpec(), prioritized);
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priority->setParam(ID::P_WIDTH, rule_count);
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cells.push_back(priority);
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RTLIL::SigBit const_if_none(std::optional<SigBit> maybe, bool polarity) {
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if (maybe)
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return *maybe;
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// Set the control signal to be constantly inactive
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if (polarity)
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return set_pol ? RTLIL::State::S0 : RTLIL::State::S1;
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else
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return reset_pol ? RTLIL::State::S0 : RTLIL::State::S1;
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}
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BitControl build(std::vector<std::optional<BitRule>>& rules) {
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std::vector<BitRule> applicable;
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int skips = 0;
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for (auto rule : rules) {
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if (rule) {
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applicable.push_back(*rule);
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} else {
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skips += 1;
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log_debug("Unused bit due to no assignment to this bit from this rule\n");
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}
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}
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log_debug("count?\n");
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if (map.count(applicable)) {
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log_debug("hit!\n");
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return map[applicable];
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Builder(RTLIL::Module* mod, RTLIL::Process* proc, bool s, bool r) : mod(mod), proc(proc), set_pol(s), reset_pol(r) {}
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std::pair<RTLIL::SigSpec, RTLIL::SigSpec> priority(const std::vector<BitRule>& applicable) {
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RTLIL::SigSpec bit_sets {};
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RTLIL::SigSpec bit_resets {};
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if (!applicable.size()) {
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return std::make_pair(bit_sets, bit_resets);
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} else if (applicable.size() == 1) {
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auto rule = applicable[0];
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if (rule.effect)
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bit_sets.append(rule.trig);
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else
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bit_resets.append(rule.trig);
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return std::make_pair(bit_sets, bit_resets);
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}
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RTLIL::Wire* prioritized = mod->addWire(NEW_ID, applicable.size());
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prioritized->attributes = proc->attributes;
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RTLIL::Cell* priority = mod->addPriority(NEW_ID, SigSpec(), prioritized);
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priority->attributes = proc->attributes;
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priority->setParam(ID::WIDTH, applicable.size());
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SigSpec bit_sets;
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SigSpec bit_resets;
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RTLIL::SigSpec priority_in;
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std::vector<RTLIL::State> priority_pol;
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// Construct applicable rules
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for (auto rule : applicable) {
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log_debug("if %s == %d then set %d\n", log_signal(rule.trig), rule.trig_polarity, rule.effect);
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prioritized->width++;
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priority_in.append(rule.trig);
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priority_pol.push_back(RTLIL::State(rule.trig_polarity));
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if (rule.effect)
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@ -223,70 +225,67 @@ void gen_dffsr(RTLIL::Module *mod, DSigs sigs, bool clk_polarity,
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bit_resets.append(SigBit(prioritized, priority_in.size() - 1));
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}
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// Stuff $priority with unused bits
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priority_in.append(Const(0, skips));
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for (int i = 0; i < skips; i++) {
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prioritized->width++;
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priority_pol.push_back(RTLIL::State::S0);
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}
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std::optional<SigBit> set;
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priority->setPort(ID::A, priority_in);
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priority->setPort(ID::Y, prioritized); // fixup (previously zero-width)
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priority->setParam(ID::POLARITY, priority_pol);
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return std::make_pair(bit_sets, bit_resets);
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}
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std::pair<RTLIL::SigBit, RTLIL::SigBit> reduce(const std::pair<RTLIL::SigSpec, RTLIL::SigSpec>& unreduced) {
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const auto& [bit_sets, bit_resets] = unreduced;
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std::optional<SigBit> set, reset;
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if (bit_sets.size()) {
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if (bit_sets.size() == 1) {
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set = bit_sets[0];
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} else {
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set = mod->addWire(NEW_ID);
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// Polarities are consistent, as guaranteed by check prior
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cells.push_back(set_pol ? mod->addReduceOr(NEW_ID, bit_sets, *set) : mod->addReduceAnd(NEW_ID, bit_sets, *set));
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set->wire->attributes = proc->attributes;
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// Polarities are required to be consistent, as guaranteed by check above buildere
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(set_pol ? mod->addReduceOr(NEW_ID, bit_sets, *set) : mod->addReduceAnd(NEW_ID, bit_sets, *set))->attributes = proc->attributes;
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}
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}
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std::optional<SigBit> reset;
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if (bit_resets.size()) {
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if (bit_resets.size() == 1) {
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reset = bit_resets[0];
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} else {
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reset = mod->addWire(NEW_ID);
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cells.push_back(reset_pol ? mod->addReduceOr(NEW_ID, bit_resets, *reset) : mod->addReduceAnd(NEW_ID, bit_resets, *reset));
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reset->wire->attributes = proc->attributes;
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(reset_pol ? mod->addReduceOr(NEW_ID, bit_resets, *reset) : mod->addReduceAnd(NEW_ID, bit_resets, *reset))->attributes = proc->attributes;
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}
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}
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if (!set)
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set = set_pol ? RTLIL::State::S0 : RTLIL::State::S1;
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if (!reset)
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reset = reset_pol ? RTLIL::State::S0 : RTLIL::State::S1;
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return std::make_pair(const_if_none(set, true), const_if_none(reset, false));
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}
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MaybeBitControl build(std::vector<std::optional<BitRule>>& rules) {
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std::vector<BitRule> applicable;
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for (auto rule : rules) {
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if (rule) {
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applicable.push_back(*rule);
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} else {
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log_debug("Unused bit due to no assignment to this bit from this rule\n");
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}
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}
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if (map.count(applicable)) {
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return map[applicable];
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}
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auto ret = std::make_pair(set, reset);
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auto priority_controls = priority(applicable);
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auto ret = reduce(priority_controls);
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map[applicable] = ret;
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return ret;
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}
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void finish(RTLIL::Process* proc) {
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prioritized->attributes = proc->attributes;
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for (auto* cell : cells)
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cell->attributes = proc->attributes;
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cells[0]->setPort(ID::A, priority_in);
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cells[0]->setPort(ID::Y, prioritized); // fixup (previously zero-width)
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cells[0]->setParam(ID::POLARITY, priority_pol);
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cells[0]->setParam(ID::WIDTH, cells[0]->getPort(ID::A).size() / cells[0]->getParam(ID::P_WIDTH).as_int());
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}
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};
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Builder builder(mod, async_rules.size(), *set_pol, *reset_pol);
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Builder builder(mod, proc, *set_pol, *reset_pol);
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for (int i = 0; i < sigs.d.size(); i++) {
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log_debug("bit %d:\n", i);
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auto [set, reset] = builder.build(bit_rules[i]);
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sig_sr_set.append(*set);
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sig_sr_clr.append(*reset);
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}
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builder.finish(proc);
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std::stringstream sstr;
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sstr << "$procdff$" << (autoidx++);
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RTLIL::Cell *cell = mod->addDffsr(sstr.str(), sigs.clk, sig_sr_set, sig_sr_clr, sigs.d, sigs.q, clk_polarity);
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cell->attributes = proc->attributes;
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cell->setParam(ID::SET_POLARITY, Const(*set_pol, 1));
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cell->setParam(ID::CLR_POLARITY, Const(*reset_pol, 1));
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log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
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cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
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}
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