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Fixed cellaigs port extending

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Clifford Wolf
2015-06-10 07:16:30 +02:00
parent 66f9ee412a
commit 85287295b2
3 changed files with 11 additions and 3 deletions
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2
kernel/cellaigs.cc
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@@ -77,7 +77,7 @@ struct AigMaker
if (portbit >= GetSize(cell->getPort(portname))) {
if (cell->parameters.count(portname.str() + "_SIGNED") && cell->getParam(portname.str() + "_SIGNED").as_bool())
return inport(portname, GetSize(cell->getPort(portname))-1, inverter);
return bool_node(!inverter);
return bool_node(inverter);
}
AigNode node;