Implement design_equal command
This commit is contained in:
Robert O'Callahan
parent
64a933d77b
commit
914e14946d
@ -5,6 +5,7 @@ endif
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OBJS += passes/cmds/add.o
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OBJS += passes/cmds/delete.o
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OBJS += passes/cmds/design.o
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OBJS += passes/cmds/design_equal.o
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OBJS += passes/cmds/select.o
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OBJS += passes/cmds/show.o
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OBJS += passes/cmds/viz.o
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352
passes/cmds/design_equal.cc
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352
passes/cmds/design_equal.cc
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@ -0,0 +1,352 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/rtlil.h"
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YOSYS_NAMESPACE_BEGIN
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class ModuleComparator
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{
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RTLIL::Module *mod_a;
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RTLIL::Module *mod_b;
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public:
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ModuleComparator(RTLIL::Module *mod_a, RTLIL::Module *mod_b) : mod_a(mod_a), mod_b(mod_b) {}
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bool compare_sigbit(const RTLIL::SigBit &a, const RTLIL::SigBit &b)
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{
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if (a.wire == nullptr && b.wire == nullptr)
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return a.data == b.data;
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if (a.wire != nullptr && b.wire != nullptr)
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return a.wire->name == b.wire->name && a.offset == b.offset;
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return false;
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}
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bool compare_sigspec(const RTLIL::SigSpec &a, const RTLIL::SigSpec &b)
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{
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if (a.size() != b.size()) return false;
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auto it_a = a.begin(), it_b = b.begin();
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for (; it_a != a.end(); ++it_a, ++it_b) {
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if (!compare_sigbit(*it_a, *it_b)) return false;
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}
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return true;
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}
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std::string compare_attributes(const RTLIL::AttrObject *a, const RTLIL::AttrObject *b)
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{
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for (const auto &it : a->attributes) {
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if (b->attributes.count(it.first) == 0)
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return "missing attribute " + std::string(log_id(it.first)) + " in second design";
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if (it.second != b->attributes.at(it.first))
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return "attribute " + std::string(log_id(it.first)) + " mismatch: " + log_const(it.second) + " != " + log_const(b->attributes.at(it.first));
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}
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for (const auto &it : b->attributes)
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if (a->attributes.count(it.first) == 0)
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return "missing attribute " + std::string(log_id(it.first)) + " in first design";
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return "";
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}
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std::string compare_wires(const RTLIL::Wire *a, const RTLIL::Wire *b)
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{
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if (a->name != b->name)
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return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name);
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if (a->width != b->width)
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return "width mismatch: " + std::to_string(a->width) + " != " + std::to_string(b->width);
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if (a->start_offset != b->start_offset)
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return "start_offset mismatch: " + std::to_string(a->start_offset) + " != " + std::to_string(b->start_offset);
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if (a->port_id != b->port_id)
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return "port_id mismatch: " + std::to_string(a->port_id) + " != " + std::to_string(b->port_id);
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if (a->port_input != b->port_input)
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return "port_input mismatch: " + std::to_string(a->port_input) + " != " + std::to_string(b->port_input);
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if (a->port_output != b->port_output)
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return "port_output mismatch: " + std::to_string(a->port_output) + " != " + std::to_string(b->port_output);
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if (a->upto != b->upto)
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return "upto mismatch: " + std::to_string(a->upto) + " != " + std::to_string(b->upto);
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if (a->is_signed != b->is_signed)
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return "is_signed mismatch: " + std::to_string(a->is_signed) + " != " + std::to_string(b->is_signed);
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if (std::string mismatch = compare_attributes(a, b); !mismatch.empty())
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return mismatch;
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return "";
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}
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void check_wires()
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{
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for (const auto &it : mod_a->wires_) {
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if (mod_b->wires_.count(it.first) == 0)
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log_error("Module %s missing wire %s in second design.\n", log_id(mod_a->name), log_id(it.first));
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if (std::string mismatch = compare_wires(it.second, mod_b->wires_.at(it.first)); !mismatch.empty())
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log_error("Module %s wire %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch);
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}
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for (const auto &it : mod_b->wires_)
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if (mod_a->wires_.count(it.first) == 0)
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log_error("Module %s missing wire %s in first design.\n", log_id(mod_b->name), log_id(it.first));
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}
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std::string compare_memories(const RTLIL::Memory *a, const RTLIL::Memory *b)
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{
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if (a->name != b->name)
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return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name);
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if (a->width != b->width)
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return "width mismatch: " + std::to_string(a->width) + " != " + std::to_string(b->width);
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if (a->start_offset != b->start_offset)
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return "start_offset mismatch: " + std::to_string(a->start_offset) + " != " + std::to_string(b->start_offset);
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if (a->size != b->size)
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return "size mismatch: " + std::to_string(a->size) + " != " + std::to_string(b->size);
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if (std::string mismatch = compare_attributes(a, b); !mismatch.empty())
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return mismatch;
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return "";
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}
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std::string compare_cells(const RTLIL::Cell *a, const RTLIL::Cell *b)
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{
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if (a->name != b->name)
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return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name);
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if (a->type != b->type)
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return "type mismatch: " + std::string(log_id(a->type)) + " != " + log_id(b->type);
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if (std::string mismatch = compare_attributes(a, b); !mismatch.empty())
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return mismatch;
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for (const auto &it : a->parameters) {
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if (b->parameters.count(it.first) == 0)
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return "parameter mismatch: missing parameter " + std::string(log_id(it.first)) + " in second design";
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if (it.second != b->parameters.at(it.first))
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return "parameter mismatch: " + std::string(log_id(it.first)) + " mismatch: " + log_const(it.second) + " != " + log_const(b->parameters.at(it.first));
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}
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for (const auto &it : b->parameters)
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if (a->parameters.count(it.first) == 0)
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return "parameter mismatch: missing parameter " + std::string(log_id(it.first)) + " in first design";
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for (const auto &it : a->connections()) {
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if (b->connections().count(it.first) == 0)
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return "connection mismatch: missing connection " + std::string(log_id(it.first)) + " in second design";
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if (!compare_sigspec(it.second, b->connections().at(it.first)))
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return "connection " + std::string(log_id(it.first)) + " mismatch: " + log_signal(it.second) + " != " + log_signal(b->connections().at(it.first));
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}
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for (const auto &it : b->connections())
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if (a->connections().count(it.first) == 0)
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return "connection mismatch: missing connection " + std::string(log_id(it.first)) + " in first design";
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return "";
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}
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void check_cells()
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{
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for (const auto &it : mod_a->cells_) {
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if (mod_b->cells_.count(it.first) == 0)
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log_error("Module %s missing cell %s in second design.\n", log_id(mod_a->name), log_id(it.first));
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if (std::string mismatch = compare_cells(it.second, mod_b->cells_.at(it.first)); !mismatch.empty())
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log_error("Module %s cell %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch);
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}
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for (const auto &it : mod_b->cells_)
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if (mod_a->cells_.count(it.first) == 0)
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log_error("Module %s missing cell %s in first design.\n", log_id(mod_b->name), log_id(it.first));
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}
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void check_memories()
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{
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for (const auto &it : mod_a->memories) {
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if (mod_b->memories.count(it.first) == 0)
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log_error("Module %s missing memory %s in second design.\n", log_id(mod_a->name), log_id(it.first));
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if (std::string mismatch = compare_memories(it.second, mod_b->memories.at(it.first)); !mismatch.empty())
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log_error("Module %s memory %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch);
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}
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for (const auto &it : mod_b->memories)
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if (mod_a->memories.count(it.first) == 0)
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log_error("Module %s missing memory %s in first design.\n", log_id(mod_b->name), log_id(it.first));
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}
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std::string compare_case_rules(const RTLIL::CaseRule *a, const RTLIL::CaseRule *b)
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{
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if (std::string mismatch = compare_attributes(a, b); !mismatch.empty()) return mismatch;
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if (a->compare.size() != b->compare.size())
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return "compare size mismatch: " + std::to_string(a->compare.size()) + " != " + std::to_string(b->compare.size());
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for (size_t i = 0; i < a->compare.size(); i++)
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if (!compare_sigspec(a->compare[i], b->compare[i]))
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return "compare " + std::to_string(i) + " mismatch: " + log_signal(a->compare[i]) + " != " + log_signal(b->compare[i]);
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if (a->actions.size() != b->actions.size())
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return "actions size mismatch: " + std::to_string(a->actions.size()) + " != " + std::to_string(b->actions.size());
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for (size_t i = 0; i < a->actions.size(); i++) {
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if (!compare_sigspec(a->actions[i].first, b->actions[i].first))
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return "action " + std::to_string(i) + " first mismatch: " + log_signal(a->actions[i].first) + " != " + log_signal(b->actions[i].first);
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if (!compare_sigspec(a->actions[i].second, b->actions[i].second))
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return "action " + std::to_string(i) + " second mismatch: " + log_signal(a->actions[i].second) + " != " + log_signal(b->actions[i].second);
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}
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if (a->switches.size() != b->switches.size())
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return "switches size mismatch: " + std::to_string(a->switches.size()) + " != " + std::to_string(b->switches.size());
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for (size_t i = 0; i < a->switches.size(); i++)
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if (std::string mismatch = compare_switch_rules(a->switches[i], b->switches[i]); !mismatch.empty())
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return "switch " + std::to_string(i) + " " + mismatch;
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return "";
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}
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std::string compare_switch_rules(const RTLIL::SwitchRule *a, const RTLIL::SwitchRule *b)
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{
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if (std::string mismatch = compare_attributes(a, b); !mismatch.empty())
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return mismatch;
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if (!compare_sigspec(a->signal, b->signal))
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return "signal mismatch: " + log_signal(a->signal) + " != " + log_signal(b->signal);
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if (a->cases.size() != b->cases.size())
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return "cases size mismatch: " + std::to_string(a->cases.size()) + " != " + std::to_string(b->cases.size());
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for (size_t i = 0; i < a->cases.size(); i++)
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if (std::string mismatch = compare_case_rules(a->cases[i], b->cases[i]); !mismatch.empty())
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return "case " + std::to_string(i) + " " + mismatch;
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return "";
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}
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std::string compare_sync_rules(const RTLIL::SyncRule *a, const RTLIL::SyncRule *b)
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{
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if (a->type != b->type)
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return "type mismatch: " + std::to_string(a->type) + " != " + std::to_string(b->type);
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if (!compare_sigspec(a->signal, b->signal))
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return "signal mismatch: " + log_signal(a->signal) + " != " + log_signal(b->signal);
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if (a->actions.size() != b->actions.size())
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return "actions size mismatch: " + std::to_string(a->actions.size()) + " != " + std::to_string(b->actions.size());
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for (size_t i = 0; i < a->actions.size(); i++) {
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if (!compare_sigspec(a->actions[i].first, b->actions[i].first))
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return "action " + std::to_string(i) + " first mismatch: " + log_signal(a->actions[i].first) + " != " + log_signal(b->actions[i].first);
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if (!compare_sigspec(a->actions[i].second, b->actions[i].second))
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return "action " + std::to_string(i) + " second mismatch: " + log_signal(a->actions[i].second) + " != " + log_signal(b->actions[i].second);
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}
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if (a->mem_write_actions.size() != b->mem_write_actions.size())
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return "mem_write_actions size mismatch: " + std::to_string(a->mem_write_actions.size()) + " != " + std::to_string(b->mem_write_actions.size());
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for (size_t i = 0; i < a->mem_write_actions.size(); i++) {
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const auto &ma = a->mem_write_actions[i];
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const auto &mb = b->mem_write_actions[i];
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if (ma.memid != mb.memid)
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return "mem_write_actions " + std::to_string(i) + " memid mismatch: " + log_id(ma.memid) + " != " + log_id(mb.memid);
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if (!compare_sigspec(ma.address, mb.address))
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return "mem_write_actions " + std::to_string(i) + " address mismatch: " + log_signal(ma.address) + " != " + log_signal(mb.address);
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if (!compare_sigspec(ma.data, mb.data))
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return "mem_write_actions " + std::to_string(i) + " data mismatch: " + log_signal(ma.data) + " != " + log_signal(mb.data);
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if (!compare_sigspec(ma.enable, mb.enable))
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return "mem_write_actions " + std::to_string(i) + " enable mismatch: " + log_signal(ma.enable) + " != " + log_signal(mb.enable);
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if (ma.priority_mask != mb.priority_mask)
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return "mem_write_actions " + std::to_string(i) + " priority_mask mismatch: " + log_const(ma.priority_mask) + " != " + log_const(mb.priority_mask);
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if (std::string mismatch = compare_attributes(&ma, &mb); !mismatch.empty())
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return "mem_write_actions " + std::to_string(i) + " " + mismatch;
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}
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return "";
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}
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std::string compare_processes(const RTLIL::Process *a, const RTLIL::Process *b)
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{
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if (a->name != b->name) return "name mismatch: " + std::string(log_id(a->name)) + " != " + log_id(b->name);
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if (std::string mismatch = compare_attributes(a, b); !mismatch.empty())
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return mismatch;
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if (std::string mismatch = compare_case_rules(&a->root_case, &b->root_case); !mismatch.empty())
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return "case rule " + mismatch;
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if (a->syncs.size() != b->syncs.size())
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return "sync count mismatch: " + std::to_string(a->syncs.size()) + " != " + std::to_string(b->syncs.size());
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for (size_t i = 0; i < a->syncs.size(); i++)
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if (std::string mismatch = compare_sync_rules(a->syncs[i], b->syncs[i]); !mismatch.empty())
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return "sync " + std::to_string(i) + " " + mismatch;
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return "";
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}
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void check_processes()
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{
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for (auto &it : mod_a->processes) {
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if (mod_b->processes.count(it.first) == 0)
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log_error("Module %s missing process %s in second design.\n", log_id(mod_a->name), log_id(it.first));
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if (std::string mismatch = compare_processes(it.second, mod_b->processes.at(it.first)); !mismatch.empty())
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log_error("Module %s process %s %s.\n", log_id(mod_a->name), log_id(it.first), mismatch.c_str());
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}
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for (auto &it : mod_b->processes)
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if (mod_a->processes.count(it.first) == 0)
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log_error("Module %s missing process %s in first design.\n", log_id(mod_b->name), log_id(it.first));
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}
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void check_connections()
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{
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const auto &conns_a = mod_a->connections();
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const auto &conns_b = mod_b->connections();
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if (conns_a.size() != conns_b.size()) {
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log_error("Module %s connection count differs: %zu != %zu\n", log_id(mod_a->name), conns_a.size(), conns_b.size());
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} else {
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for (size_t i = 0; i < conns_a.size(); i++) {
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if (!compare_sigspec(conns_a[i].first, conns_b[i].first))
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log_error("Module %s connection %zu LHS %s != %s.\n", log_id(mod_a->name), i, log_signal(conns_a[i].first), log_signal(conns_b[i].first));
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if (!compare_sigspec(conns_a[i].second, conns_b[i].second))
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log_error("Module %s connection %zu RHS %s != %s.\n", log_id(mod_a->name), i, log_signal(conns_a[i].second), log_signal(conns_b[i].second));
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}
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}
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}
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void check()
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{
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if (mod_a->name != mod_b->name)
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log_error("Modules have different names: %s != %s\n", log_id(mod_a->name), log_id(mod_b->name));
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if (std::string mismatch = compare_attributes(mod_a, mod_b); !mismatch.empty())
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log_error("Module %s %s.\n", log_id(mod_a->name), mismatch);
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check_wires();
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check_cells();
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check_memories();
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check_connections();
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check_processes();
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}
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};
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struct DesignEqualPass : public Pass {
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DesignEqualPass() : Pass("design_equal", "check if two designs are the same") { }
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void help() override
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{
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log("\n");
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log(" design_equal <name>\n");
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log("\n");
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log("Compare the current design with the design previously saved under the given\n");
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log("name. Abort with an error if the designs are different.\n");
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log("\n");
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}
|
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
if (args.size() != 2)
|
||||
log_cmd_error("Missing argument.\n");
|
||||
|
||||
std::string check_name = args[1];
|
||||
if (saved_designs.count(check_name) == 0)
|
||||
log_cmd_error("No saved design '%s' found!\n", check_name.c_str());
|
||||
|
||||
RTLIL::Design *other = saved_designs.at(check_name);
|
||||
|
||||
for (auto &it : design->modules_) {
|
||||
RTLIL::Module *mod = it.second;
|
||||
if (!other->has(mod->name))
|
||||
log_error("Second design missing module %s.\n", log_id(mod->name));
|
||||
|
||||
ModuleComparator cmp(mod, other->module(mod->name));
|
||||
cmp.check();
|
||||
}
|
||||
for (auto &it : other->modules_) {
|
||||
RTLIL::Module *mod = it.second;
|
||||
if (!design->has(mod->name))
|
||||
log_error("First design missing module %s.\n", log_id(mod->name));
|
||||
}
|
||||
|
||||
log("Designs are identical.\n");
|
||||
}
|
||||
} DesignEqualPass;
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
22
tests/various/design_equal_fail.ys
Normal file
22
tests/various/design_equal_fail.ys
Normal file
@ -0,0 +1,22 @@
|
||||
logger -expect error "Second design missing module top_renamed" 1
|
||||
|
||||
read_rtlil <<EOT
|
||||
module \top
|
||||
wire width 1 input 1 \a
|
||||
wire width 1 output 2 \y
|
||||
connect \y \a
|
||||
end
|
||||
EOT
|
||||
|
||||
design -save golden
|
||||
|
||||
design -reset
|
||||
read_rtlil <<EOT
|
||||
module \top_renamed
|
||||
wire width 1 input 1 \a
|
||||
wire width 1 output 2 \y
|
||||
connect \y \a
|
||||
end
|
||||
EOT
|
||||
|
||||
design_equal golden
|
||||
17
tests/various/design_equal_pass.ys
Normal file
17
tests/various/design_equal_pass.ys
Normal file
@ -0,0 +1,17 @@
|
||||
read_rtlil <<EOT
|
||||
module \top
|
||||
wire width 1 input 1 \a
|
||||
wire width 1 output 2 \y
|
||||
connect \y \a
|
||||
end
|
||||
EOT
|
||||
|
||||
design -save golden
|
||||
design_equal golden
|
||||
|
||||
design -save copy
|
||||
design_equal copy
|
||||
|
||||
design -load golden
|
||||
design_equal golden
|
||||
design_equal copy
|
||||
Loading…
x
Reference in New Issue
Block a user