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cellhelp: Add source line to help

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Include Source file and line number in SimHelper struct, and use it for verilog code caption in rst dump.
Also reformat python string conversion to iterate over a list of fields instead of repeating code for each.
This commit is contained in:
Krystine Sherwin
2024-04-12 13:57:51 +12:00
parent 784292626e
commit a2b2904ed8
2 changed files with 18 additions and 7 deletions
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4
kernel/register.cc
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@@ -757,6 +757,7 @@ struct SimHelper {
}
string title;
string ports;
string source;
string desc;
string code;
string ver;
@@ -901,7 +902,8 @@ struct HelpPass : public Pass {
// source code
fprintf(f, "Simulation model (Verilog)\n");
fprintf(f, "--------------------------\n\n");
fprintf(f, ".. code:: verilog\n\n");
fprintf(f, ".. code-block:: verilog\n");
fprintf(f, " :caption: %s\n\n", cell.source.c_str());
std::stringstream ss;
ss << cell.code;
for (std::string line; std::getline(ss, line, '\n');) {