sf2: fix name of AND modules
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committed by
Marcelina Kościelnicka
parent
0b05452cf7
commit
a58571d0fe
@@ -1,20 +1,20 @@
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// https://coredocs.s3.amazonaws.com/Libero/12_0_0/Tool/sf2_mlg.pdf
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module ADD2 (
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module AND2 (
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input A, B,
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output Y
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);
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assign Y = A & B;
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endmodule
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module ADD3 (
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module AND3 (
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input A, B, C,
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output Y
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);
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assign Y = A & B & C;
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endmodule
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module ADD4 (
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module AND4 (
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input A, B, C, D,
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output Y
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);
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