github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-04-27 20:49:44 +00:00
Code Issues Releases Wiki Activity

Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)

Browse Source
This commit is contained in:
Clifford Wolf
2014-02-03 13:01:45 +01:00
parent de9226a64f
commit a6750b3753
11 changed files with 186 additions and 78 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
kernel/rtlil.cc
View File

@@ -556,6 +556,7 @@ namespace {
param("\\MEMID");
param("\\CLK_ENABLE");
param("\\CLK_POLARITY");
param("\\TRANSPARENT");
port("\\CLK", 1);
port("\\ADDR", param("\\ABITS"));
port("\\DATA", param("\\WIDTH"));
@@ -582,6 +583,7 @@ namespace {
param("\\OFFSET");
param("\\RD_CLK_ENABLE");
param("\\RD_CLK_POLARITY");
param("\\RD_TRANSPARENT");
param("\\WR_CLK_ENABLE");
param("\\WR_CLK_POLARITY");
port("\\RD_CLK", param("\\RD_PORTS"));