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Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort

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write_rtlil: don't sort
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Emil J
2025-09-22 11:14:39 +02:00
committed by GitHub
parent b9dc578411 0d8c21129f
commit a78eb9e151
19 changed files with 247 additions and 109 deletions
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techlibs/fabulous/synth_fabulous.cc
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@@ -69,7 +69,7 @@ struct SynthPass : public ScriptPass
log(" use the specified Verilog file for extra primitives (can be specified multiple\n");
log(" times).\n");
log("\n");
log(" -extra-map <techamp.v>\n");
log(" -extra-map <techmap.v>\n");
log(" use the specified Verilog file for extra techmap rules (can be specified multiple\n");
log(" times).\n");
log("\n");