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Remember global declarations and defines accross read_verilog calls

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Clifford Wolf
2016-11-15 12:42:43 +01:00
parent a2206180d6
commit a926a6afc2
6 changed files with 23 additions and 8 deletions
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2
kernel/rtlil.cc
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@@ -306,6 +306,8 @@ RTLIL::Design::~Design()
delete it->second;
for (auto n : verilog_packages)
delete n;
for (auto n : verilog_globals)
delete n;
}
RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()

3
kernel/rtlil.h
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@@ -793,7 +793,8 @@ struct RTLIL::Design
int refcount_modules_;
dict<RTLIL::IdString, RTLIL::Module*> modules_;
std::vector<AST::AstNode*> verilog_packages;
std::vector<AST::AstNode*> verilog_packages, verilog_globals;
dict<std::string, std::pair<std::string, bool>> verilog_defines;
std::vector<RTLIL::Selection> selection_stack;
dict<RTLIL::IdString, RTLIL::Selection> selection_vars;