From b2270ae1c888a29712c99f7c658ffc1cb3ee83e1 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 1 Dec 2025 19:40:58 +0100
Subject: [PATCH] aiger2: fix case where submodule cell input port has empty
 SigSpec

---
 backends/aiger2/aiger.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc
index 499dfd22d..babc29826 100644
--- a/backends/aiger2/aiger.cc
+++ b/backends/aiger2/aiger.cc
@@ -849,7 +849,7 @@ struct XAigerAnalysis : Index<XAigerAnalysis, int, 0, 0> {
 		for (auto wire : mod->wires()) {
 			if (wire->port_input && !wire->port_output) {
 				SigSpec port = driver->getPort(wire->name);
-				for (int i = 0; i < wire->width; i++) {
+				for (int i = 0; i < std::min(wire->width, port.size()); i++) {
 					int ilevel = visit(cursor, port[i]);
 					max = std::max(max, ilevel + 1);
 				}