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mirror of synced 2026-05-04 23:27:07 +00:00

Move Pass::call() out of abc9_ops into abc9

This commit is contained in:
Eddie Hung
2019-12-30 19:23:54 -08:00
parent 88334cab89
commit b42b64e8ed
3 changed files with 63 additions and 68 deletions

View File

@@ -710,6 +710,10 @@ struct XAigerWriter
RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
log_assert(holes_module);
for (auto cell : holes_module->cells())
if (!cell->type.in("$_NOT_", "$_AND_"))
log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
module->design->selection_stack.emplace_back(false);
module->design->selection().select(holes_module);