From b6c148f84a5f08f73e23c187148261cff9301e4f Mon Sep 17 00:00:00 2001 From: Natalia Date: Wed, 28 Jan 2026 22:46:10 -0800 Subject: [PATCH] tests/verific: ensure mixed -f requires VHDL unit --- tests/verific/mixed_flist.sv | 3 ++- tests/verific/mixed_flist.ys | 3 +-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/verific/mixed_flist.sv b/tests/verific/mixed_flist.sv index 83c04054f..28e073891 100644 --- a/tests/verific/mixed_flist.sv +++ b/tests/verific/mixed_flist.sv @@ -1,3 +1,4 @@ module sv_top(input logic a, output logic y); - assign y = a; + // Instantiates VHDL entity to ensure mixed -f list is required + vhdl_mod u_vhdl(.a(a), .y(y)); endmodule diff --git a/tests/verific/mixed_flist.ys b/tests/verific/mixed_flist.ys index 59849a5e5..9f5fe607a 100644 --- a/tests/verific/mixed_flist.ys +++ b/tests/verific/mixed_flist.ys @@ -1,4 +1,3 @@ verific -f -sv mixed_flist.flist -verific -import -all +verific -import sv_top select -assert-mod-count 1 sv_top -select -assert-mod-count 2 =*