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proc_rmdead: use explicit pattern set when there are no wildcards

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If width of a case expression was large, explicit patterns could cause
the existing logic to take an extremely long time, or exhaust the
maximum size of the underlying set. For cases where all of the patterns
are fully defined and there are no constants in the case expression,
this change uses a simple set to track which patterns have been seen.
This commit is contained in:
Zachary Snow
2021-07-28 17:34:24 -04:00
committed by Zachary Snow
parent 4fec3a85cd
commit c016f6a423
4 changed files with 386 additions and 2 deletions
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46
tests/proc/rmdead.v Normal file
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module top (
input wire signed x,
output reg [31:0] y
);
wire signed fail = ~x;
always @*
case (x)
1'b0: y = 0;
1'b1: y = 1;
default: y = fail;
endcase
always @*
case (x)
2'sb00: y = 0;
2'sb00: y = fail;
endcase
always @*
case (x)
2'sb00: y = 0;
default: y = fail;
2'sb01: y = 1;
2'sb10: y = 2;
2'sb11: y = 3;
2'sb00: y = fail;
2'sb01: y = fail;
2'sb10: y = fail;
2'sb11: y = fail;
endcase
always @*
case ({x, x})
2'b00: y = 0;
2'b01: y = 1;
2'b10: y = 2;
2'b11: y = 3;
default: y = fail;
2'b00: y = fail;
2'b01: y = fail;
2'b10: y = fail;
2'b11: y = fail;
endcase
endmodule

4
tests/proc/rmdead.ys Normal file
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read_verilog rmdead.v
proc
opt_clean
select -assert-count 0 w:fail