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verilog: improve string literal matching speed (fixes #5076)

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Use a greedy regular expression to match input inside a string
literal, so that flex can accumulate a longer match instead of
invoking a rule for each individual character.
This commit is contained in:
Gary Wong
2025-05-31 22:38:44 -06:00
parent 86282027c0
commit ca7d94af99
1 changed files with 1 additions and 2 deletions
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3
frontends/verilog/verilog_lexer.l
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@@ -336,7 +336,7 @@ TIME_SCALE_SUFFIX [munpf]?s
} }
\" { BEGIN(STRING); } \" { BEGIN(STRING); }
<STRING>\\. { yymore(); real_location = old_location; } <STRING>([^\"]|\\.)+ { yymore(); real_location = old_location; }
<STRING>\" { <STRING>\" {
BEGIN(0); BEGIN(0);
char *yystr = strdup(yytext); char *yystr = strdup(yytext);
@@ -376,7 +376,6 @@ TIME_SCALE_SUFFIX [munpf]?s
free(yystr); free(yystr);
return TOK_STRING; return TOK_STRING;
} }
<STRING>. { yymore(); real_location = old_location; }
and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 { and|nand|or|nor|xor|xnor|not|buf|bufif0|bufif1|notif0|notif1 {
yylval->string = new std::string(yytext); yylval->string = new std::string(yytext);