verilog: ignore ranges too without -specify

tests/various/specify.v

@@ -55,3 +55,10 @@ specify
   $setup(d, posedge clk &&& e, 1:2:3);
 endspecify
 endmodule
+
+module test6(input clk, d, e, output q);
+specify
+  (d[0] *> q[0]) = (3,1);
+  (posedge clk[0] => (q[0] +: d[0])) = (3,1);
+endspecify
+endmodule