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verilog_backend: alter only design copy unless -wreck

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This commit is contained in:
Emil J. Tywoniak 2026-01-19 19:51:09 +01:00
parent f785b664af
commit dcd73b6b03
1 changed files with 30 additions and 2 deletions
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32
backends/verilog/verilog_backend.cc
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@ -95,7 +95,7 @@ bool VERILOG_BACKEND::id_is_verilog_escaped(const std::string &str) {
PRIVATE_NAMESPACE_BEGIN
bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, extmem, defparam, decimal, siminit, systemverilog, simple_lhs, noparallelcase;
bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, extmem, defparam, decimal, siminit, systemverilog, simple_lhs, noparallelcase, wreck;
int auto_name_counter, auto_name_offset, auto_name_digits, extmem_counter;
dict<RTLIL::IdString, int> auto_name_map;
std::set<RTLIL::IdString> reg_wires;
@ -2554,6 +2554,10 @@ struct VerilogBackend : public Backend {
log(" only write selected modules. modules must be selected entirely or\n");
log(" not at all.\n");
log("\n");
log(" -wreck\n");
log(" wreck your design by running required preparation passes\n");
log(" on it, instead of a copy. Used to be the default.\n");
log("\n");
log(" -v\n");
log(" verbose output (print new names of all renamed wires and cells)\n");
log("\n");
@ -2666,6 +2670,10 @@ struct VerilogBackend : public Backend {
verbose = true;
continue;
}
if (arg == "-wreck") {
wreck = true;
continue;
}
break;
}
extra_args(f, filename, args, argidx);
@ -2676,6 +2684,21 @@ struct VerilogBackend : public Backend {
extmem_prefix = filename.substr(0, filename.rfind('.'));
}
RTLIL::Design *original_design;
if (!wreck) {
// FIXME shamefully copied out of design.cc
RTLIL::Design * design_copy = new RTLIL::Design;
for (auto mod : design->modules())
design_copy->add(mod->clone());
design_copy->selection_stack = design->selection_stack;
design_copy->selection_vars = design->selection_vars;
design_copy->selected_active_module = design->selected_active_module;
original_design = design;
design = design_copy;
}
log_push();
if (!noexpr) {
Pass::call(design, "bmuxmap");
@ -2685,7 +2708,7 @@ struct VerilogBackend : public Backend {
Pass::call(design, "clean_zerowidth");
log_pop();
design->sort_modules();
design->sort_modules();
*f << stringf("/* Generated by %s */\n", yosys_maybe_version());
@ -2702,6 +2725,11 @@ struct VerilogBackend : public Backend {
dump_module(*f, "", module);
}
if (!wreck) {
RTLIL::Design * design_copy = design;
design = original_design;
delete design_copy;
}
auto_name_map.clear();
reg_wires.clear();
}