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mirror of synced 2026-04-25 20:02:10 +00:00

Fix formatting for msys2 mingw build using GetSize

This commit is contained in:
Miodrag Milanovic
2019-07-31 11:49:48 +02:00
committed by Clifford Wolf
parent 82a2972068
commit e9c5f1b346
8 changed files with 20 additions and 17 deletions

View File

@@ -50,7 +50,7 @@ struct AnlogicDetermineInitPass : public Pass {
extra_args(args, args.size(), design);
size_t cnt = 0;
int cnt = 0;
for (auto module : design->selected_modules())
{
for (auto cell : module->selected_cells())
@@ -65,7 +65,7 @@ struct AnlogicDetermineInitPass : public Pass {
}
}
}
log_header(design, "Updated %lu cells with determined init value.\n", cnt);
log_header(design, "Updated %d cells with determined init value.\n", cnt);
}
} AnlogicDetermineInitPass;

View File

@@ -69,7 +69,7 @@ struct AnlogicEqnPass : public Pass {
extra_args(args, args.size(), design);
size_t cnt = 0;
int cnt = 0;
for (auto module : design->selected_modules())
{
for (auto cell : module->selected_cells())
@@ -106,7 +106,7 @@ struct AnlogicEqnPass : public Pass {
}
}
}
log_header(design, "Updated %lu of AL_MAP_LUT* elements with equation.\n", cnt);
log_header(design, "Updated %d of AL_MAP_LUT* elements with equation.\n", cnt);
}
} AnlogicEqnPass;

View File

@@ -50,7 +50,7 @@ struct DetermineInitPass : public Pass {
extra_args(args, args.size(), design);
size_t cnt = 0;
int cnt = 0;
for (auto module : design->selected_modules())
{
for (auto cell : module->selected_cells())
@@ -65,7 +65,7 @@ struct DetermineInitPass : public Pass {
}
}
}
log_header(design, "Updated %lu cells with determined init value.\n", cnt);
log_header(design, "Updated %d cells with determined init value.\n", cnt);
}
} DetermineInitPass;