Merge branch 'xaig' into xc7mux

techlibs/ice40/cells_sim.v

@@ -149,7 +149,7 @@ module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) in
 	always @(posedge C)
 		Q <= D;
 `else
-    always @* Q = D;
+    always @* Q <= D;
 `endif
 endmodule
 

techlibs/xilinx/synth_xilinx.cc

@@ -294,6 +294,7 @@ struct SynthXilinxPass : public ScriptPass
 			else
 				run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 			run("clean");
+
 			// This shregmap call infers fixed length shift registers after abc
 			//   has performed any necessary retiming
 			if (!nosrl || help_mode)