github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-04-25 20:02:10 +00:00
Code Issues Releases Wiki Activity

verilog: fix specify src attribute

Browse Source
This commit is contained in:
Eddie Hung
2020-05-04 10:53:06 -07:00
parent 584780d776
commit eb5eb60fd4
2 changed files with 26 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
tests/various/specify.ys
View File

@@ -4,10 +4,16 @@ cd test
select t:$specify2 -assert-count 0
select t:$specify3 -assert-count 1
select t:$specrule -assert-count 2
select t:$specify3 a:src=specify.v:10.3-10.49 %i -assert-count 1
select t:$specrule a:src=specify.v:11.3-11.36 %i -assert-count 1
select t:$specrule a:src=specify.v:12.3-12.35 %i -assert-count 1
cd test2
select t:$specify2 -assert-count 2
select t:$specify3 -assert-count 0
select t:$specrule -assert-count 0
select t:$specify2 a:src=specify.v:26.3-26.20 %i -assert-count 1
# ^^ Note use of macro
select t:$specify2 a:src=specify.v:28.3-28.18 %i -assert-count 1
cd
write_verilog specify.out
design -stash gold