From eb6dd47bd6d6ed7ff67ffa9abac7b015d07aa1e1 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 26 Mar 2026 19:42:33 +0100 Subject: [PATCH] timinginfo: special-case $specify2 in signorm invariant --- kernel/rtlil_bufnorm.cc | 2 +- kernel/timinginfo.h | 7 +++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/kernel/rtlil_bufnorm.cc b/kernel/rtlil_bufnorm.cc index baa9e884f..3e75398be 100644 --- a/kernel/rtlil_bufnorm.cc +++ b/kernel/rtlil_bufnorm.cc @@ -1058,7 +1058,7 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname) void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal) { bool is_input_port = false; - if (module->sig_norm_index != nullptr) { + if (module->sig_norm_index != nullptr && type != ID($specify2) && type != ID($specify3) && type != ID($specrule)) { module->sig_norm_index->sigmap.apply(signal); auto dir = port_dir(portname); diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h index 9be89b54b..e2e094b62 100644 --- a/kernel/timinginfo.h +++ b/kernel/timinginfo.h @@ -106,10 +106,9 @@ struct TimingInfo for (const auto &c : src.chunks()) if (!c.wire || !c.wire->port_input) log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", module, cell, log_signal(src)); - // TODO disabled check because signorm breaks this assumption - // for (const auto &c : dst.chunks()) - // if (!c.wire || !c.wire->port_output) - // log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", module, cell, log_signal(dst)); + for (const auto &c : dst.chunks()) + if (!c.wire || !c.wire->port_output) + log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", module, cell, log_signal(dst)); int rise_max = cell->getParam(ID::T_RISE_MAX).as_int(); int fall_max = cell->getParam(ID::T_FALL_MAX).as_int(); int max = std::max(rise_max,fall_max);