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Support module/package/interface/block scope for typedef names.

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Peter Crozier
2020-03-23 20:07:22 +00:00
parent b86905d952
commit ecc22f7fed
6 changed files with 64 additions and 23 deletions
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README.md
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@@ -541,8 +541,6 @@ from SystemVerilog:
SystemVerilog files being read into the same design afterwards.
- typedefs are supported (including inside packages)
- type identifiers must currently be enclosed in (parentheses) when declaring
signals of that type (this is syntactically incorrect SystemVerilog)
- type casts are currently not supported
- enums are supported (including inside packages)