github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-02 22:34:25 +00:00
Code Issues Releases Wiki Activity

Correct a typo in the manual

Browse Source 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This commit is contained in:
YRabbit
2022-02-02 21:14:38 +10:00
parent 0a6e2bd5d5
commit f5609d52c4
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
passes/techmap/iopadmap.cc
View File

@@ -46,7 +46,7 @@ struct IopadmapPass : public Pass {
log(" -inpad <celltype> <in_port>[:<ext_port>]\n");
log(" Map module input ports to the given cell type with the\n");
log(" given output port name. if a 2nd portname is given, the\n");
log(" signal is passed through the pad call, using the 2nd\n");
log(" signal is passed through the pad cell, using the 2nd\n");
log(" portname as the port facing the module port.\n");
log("\n");
log(" -outpad <celltype> <out_port>[:<ext_port>]\n");