github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-05-02 22:34:25 +00:00
Code Issues Releases Wiki Activity

memory_share: Fix SAT-based sharing for wide ports.

Browse Source 
Fixes #3117.
This commit is contained in:
Marcelina Kościelnicka
2021-12-20 17:10:30 +01:00
parent f599c148c5
commit f84c9d8e17
2 changed files with 37 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
passes/memory/memory_share.cc
View File

@@ -416,7 +416,9 @@ struct MemoryShareWorker
else
this_addr.extend_u0(GetSize(last_addr));
port1.addr = module->Mux(NEW_ID, last_addr, this_addr, this_en_active);
SigSpec new_addr = module->Mux(NEW_ID, last_addr.extract_end(port1.wide_log2), this_addr.extract_end(port1.wide_log2), this_en_active);
port1.addr = SigSpec({new_addr, port1.addr.extract(0, port1.wide_log2)});
port1.data = module->Mux(NEW_ID, last_data, this_data, this_en_active);
std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;