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Refactoring: Renamed RTLIL::Module::wires to wires_

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Clifford Wolf
2014-07-27 01:49:51 +02:00
parent d7916a49af
commit f9946232ad
50 changed files with 191 additions and 191 deletions
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kernel/driver.cc
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@@ -243,7 +243,7 @@ static char *readline_obj_generator(const char *text, int state)
{
RTLIL::Module *module = design->modules.at(design->selected_active_module);
for (auto &it : module->wires)
for (auto &it : module->wires_)
if (RTLIL::unescape_id(it.first).substr(0, len) == text)
obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str())));