WIP merging synth phases with example

Replace `typical_phases.rst` and `examples.rst` with a single `example_synth.rst`.
Also updating the counter example to match.

Aims to reduce redundancy, and simplify the getting started section.
Details on things like `proc`, `memory` and `fsm` should instead be in the advanced section (under the new `synth` subsection).

docs/source/code_examples/intro/Makefile

@@ -2,7 +2,7 @@ PROGRAM_PREFIX :=
 
 YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
 
-DOTS = counter_00.dot counter_01.dot counter_02.dot counter_03.dot
+DOTS = counter_00.dot counter_proc.dot counter_01.dot counter_02.dot counter_03.dot
 
 dots: $(DOTS)
 

docs/source/code_examples/intro/counter_outputs.ys

@@ -1,12 +1,13 @@
-# read design
+# read
 read_verilog counter.v
 hierarchy -check -top counter
-
 show -notitle -format dot -prefix counter_00
 
-# the high-level stuff
-proc; opt; memory; opt; fsm; opt
+# elaborate
+proc
+show -notitle -format dot -prefix counter_proc
 
+opt
 show -notitle -format dot -prefix counter_01
 
 # mapping to internal cell library