Merge branch 'xaig' into xc7mux

passes/techmap/abc9.cc

@@ -414,8 +414,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 	RTLIL::Selection& sel = design->selection_stack.back();
 	sel.select(module);
 
-	// Adopt same behaviour as abc
-	// TODO: How to specify don't-care to abc9?
+	// Behave as for "abc" where BLIF writer implicitly outputs all undef as zero
 	Pass::call(design, "setundef -zero");
 
 	Pass::call(design, "aigmap");