github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-04-25 20:02:10 +00:00
Code Issues Releases Wiki Activity

Add ConstEval defaultval feature

Browse Source
This commit is contained in:
Clifford Wolf
2017-04-05 11:25:22 +02:00
parent dee4ec1661
commit fcb274a564
1 changed files with 8 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
kernel/consteval.h
View File

@@ -36,8 +36,9 @@ struct ConstEval
SigSet<RTLIL::Cell*> sig2driver;
std::set<RTLIL::Cell*> busy;
std::vector<SigMap> stack;
RTLIL::State defaultval;
ConstEval(RTLIL::Module *module) : module(module), assign_map(module)
ConstEval(RTLIL::Module *module, RTLIL::State defaultval = RTLIL::State::Sm) : module(module), assign_map(module), defaultval(defaultval)
{
CellTypes ct;
ct.setup_internals();
@@ -365,6 +366,12 @@ struct ConstEval
if (sig.is_fully_const())
return true;
if (defaultval != RTLIL::State::Sm) {
for (auto &bit : sig)
if (bit.wire) bit = defaultval;
return true;
}
for (auto &c : sig.chunks())
if (c.wire != NULL)
undef.append(c);