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Commit Graph

  • 57b4e16acd sim: Include $display output in JSON summary Jannis Harder 2023-09-22 17:52:25 +02:00
  • eeadbb583e Merge pull request #4069 from daglem/simplify-array-slice-assignment Martin Povišer 2024-01-11 11:41:34 +01:00
  • 1a4bea82a1 Merge branch 'YosysHQ:master' into master hakan-demirli 2024-01-11 09:33:53 +03:00
  • f26495e54d Bump version github-actions[bot] 2024-01-11 00:16:28 +00:00
  • e0566eafdb Add test for rhs sign extension in array slice assignment Dag Lem 2023-12-12 14:16:45 +01:00
  • 23cd23efc5 Simplify and correct AST for array slice assignment Dag Lem 2023-12-12 13:37:34 +01:00
  • a921f5968e Merge pull request #3875 from daglem/nowrshmsk-optimization Martin Povišer 2024-01-10 21:08:17 +01:00
  • 1a2b4759e8 Assign from rvalue via temporary register in nowrshmsk CASE Dag Lem 2023-12-08 20:47:43 +01:00
  • dbec704b49 Include x bits in test of lhs dynamic part-select Dag Lem 2023-12-07 13:45:56 +01:00
  • a105d2c050 Add torture test for (* nowrshmsk *) stride optimization Dag Lem 2023-11-22 06:52:04 +01:00
  • 2cab4ff173 Correction and optimization of nowrshmsk Dag Lem 2023-08-04 23:45:47 +02:00
  • e131a7895a Bump version github-actions[bot] 2024-01-10 00:16:19 +00:00
  • 6f7f71fe03 read_blif: Represent sequential elements with gate cells Martin Povišer 2024-01-09 19:31:11 +01:00
  • bc9206f0f5 write_verilog: emit casez as if/elif/else whenever possible. Catherine 2023-12-21 02:02:39 +00:00
  • 9e3d132050 Merge pull request #4121 from YosysHQ/macos_upgrade Miodrag Milanović 2024-01-09 15:05:15 +01:00
  • f6e36f0e54 cxxrtl: implement a generic record/replay interface. Catherine 2023-12-01 16:01:28 +00:00
  • a59d477098 cxxrtl: improve robustness of cxxrtl::time. Catherine 2024-01-05 20:09:49 +00:00
  • 5aaf1f1d39 cxxrtl: implement value.get() and value.set() for signed types. Catherine 2024-01-05 21:31:08 +00:00
  • c045c9a5c9 Update macOS to Ventura Miodrag Milanovic 2024-01-09 10:58:31 +01:00
  • 22370ad21e Bump version github-actions[bot] 2024-01-09 00:16:54 +00:00
  • 5a4db62870 Merge pull request #4111 from povik/verilog-back-nonpruned-case N. Engelhardt 2024-01-08 16:38:56 +01:00
  • e093f57c10 fix: fail if neither HOME nor XDG_STATE_HOME are set hakan-demirli 2024-01-08 08:49:04 +03:00
  • eb5da87d52 example_synth: hardware mapping Krystine Sherwin 2024-01-08 16:59:03 +13:00
  • e6f8804e6a example_synth: more on DSP mapping Krystine Sherwin 2024-01-08 13:24:52 +13:00
  • 54c3b63d24 fix: third time is the charm hakan-demirli 2024-01-07 14:34:27 +03:00
  • 31b45c9555 fix: xdg spec for hist hakan-demirli 2024-01-07 14:17:48 +03:00
  • bcf1c7b879 Merge branch 'YosysHQ:master' into master hakan-demirli 2024-01-07 14:08:35 +03:00
  • 82fca50309 write_verilog: Handle edge case with non-pruned processes Martin Povišer 2024-01-06 16:44:36 +01:00
  • 1ddb0892c1 Merge pull request #4101 from YosysHQ/micko/fix_init_order Martin Povišer 2024-01-06 10:46:34 +01:00
  • 30b795601c Bump version github-actions[bot] 2024-01-06 00:16:22 +00:00
  • f9dc1a2184 cxxrtl: fix comment wording. NFC Catherine 2024-01-05 20:18:36 +00:00
  • 3e358d9bfa cxxrtl: add a way to observe state changes during the commit step. Catherine 2023-10-25 10:51:39 +00:00
  • a94fafa8fe cxxrtl: add a representation of simulation timestamps. Catherine 2023-12-08 18:21:19 +00:00
  • c72dc15f02 Merge pull request #4104 from daglem/struct-hierarchical-path Martin Povišer 2024-01-05 10:38:36 +01:00
  • a96c257b3f celledges: Add messy rules that do pass the tests Martin Povišer 2023-12-11 21:36:00 +01:00
  • 1bbea13f80 Correct hierarchical path names for structs and unions Dag Lem 2024-01-04 17:22:07 +01:00
  • 3e653fe4a6 docs: more on wreduce in synth starter Krystine Sherwin 2024-01-04 12:49:48 +13:00
  • 9f1c445fbf docs: work on example_synth Krystine Sherwin 2024-01-03 11:47:33 +13:00
  • 627fbc3477 Fix Windows build by forcing initialization order, fixes #4068 Miodrag Milanovic 2024-01-02 11:26:48 +01:00
  • df65634e07 Bump version github-actions[bot] 2023-12-30 00:15:15 +00:00
  • 04fdb456f2 Merge pull request #4097 from YosysHQ/claire/constexpr Claire Xen 2023-12-29 21:31:54 +01:00
  • fb72dc1a40 Add constexpr hashlib default constructors Claire Xenia Wolf 2023-12-29 19:20:44 +01:00
  • ea7818d31b Bump version github-actions[bot] 2023-12-22 00:15:54 +00:00
  • f50e8a3c1b Follow the XDG Base Directory Specification hakan-demirli 2023-12-21 21:44:02 +03:00
  • 86b8a1c5ae Merge pull request #4087 from povik/lattice-dp8kc-fix Miodrag Milanović 2023-12-21 11:46:11 +01:00
  • c028f25158 lattice: Disable broken port configuration in bram inference Martin Povišer 2023-12-21 10:22:52 +01:00
  • fc5c5172f8 lattice: Fix mapping onto DP8KC for data width 1 or 2 Martin Povišer 2023-12-20 23:23:02 +01:00
  • 50d8c1b258 First pass example_synth done Krystine Sherwin 2023-12-20 14:08:06 +13:00
  • a4ad7cb81a Merge pull request #4049 from pepijndevos/patch-3 Miodrag Milanović 2023-12-19 08:16:54 +01:00
  • d87bd7ca3f Merge pull request #3887 from kivikakk/env-bash N. Engelhardt 2023-12-18 16:33:35 +01:00
  • 78541be4d8 Merge pull request #3971 from povik/equiv_simple-fixes N. Engelhardt 2023-12-18 16:31:02 +01:00
  • 2615209dc1 Merge pull request #4078 from jix/smtbmc-cexenum-support N. Engelhardt 2023-12-18 16:20:52 +01:00
  • a33b1b6059 More work on example_synth Krystine Sherwin 2023-12-18 17:49:15 +13:00
  • 742ec78ca3 Switching example synth to fifo Krystine Sherwin 2023-12-18 13:19:01 +13:00
  • 70d35314db Bump version github-actions[bot] 2023-12-15 00:16:38 +00:00
  • 94d7c22714 yosys-witness: Add aiw2yw --present-only to omit unused signals Jannis Harder 2023-12-14 16:45:19 +01:00
  • 3fab4d42ec smtbmc: Allow raw SMT-LIBv2 comamnds and expressions for --incremental Jannis Harder 2023-12-14 16:44:21 +01:00
  • 111085669b smtbmc: Use fewer smt commands while writing .yw traces Jannis Harder 2023-12-14 16:42:48 +01:00
  • 449e3dbbd3 cxxrtl: Mask bmux result appropriately Martin Povišer 2023-12-13 18:21:37 +01:00
  • 80c78aaad6 New example_synth code Krystine Sherwin 2023-12-14 16:21:52 +13:00
  • 39fdde87a7 Bump version github-actions[bot] 2023-12-14 00:16:03 +00:00
  • 6d1caf6134 Initial synth_ice40 example Krystine Sherwin 2023-12-14 11:30:51 +13:00
  • 3a153f99db Add cell_libs.rst Krystine Sherwin 2023-12-14 10:08:46 +13:00
  • 112b11116d Merge pull request #4072 from merryhime/cxxrtl-value-tests Martin Povišer 2023-12-13 18:11:26 +01:00
  • 1dff3c83d9 tests/cxxrtl: Add -O2 Merry 2023-12-13 12:27:06 +00:00
  • 29e0cc6acd cxxrtl: Add simple fuzzing tests for value Merry 2023-12-13 12:18:13 +00:00
  • d7cb6981b5 cxxrtl: Fix value::ctlz Merry 2023-12-13 12:15:12 +00:00
  • ded63bedd5 cxxrtl: Fix value::sshr Merry 2023-12-13 12:11:57 +00:00
  • ff53f3d2b6 cxxrtl: Fix value::shl Merry 2023-12-13 12:02:30 +00:00
  • 1c8e58a736 cxxrtl: Fix formating Henri Nurmi 2023-12-10 08:15:41 +02:00
  • 79c0bfcb22 cxxrtl: Remove unnecessary length check Henri Nurmi 2023-12-10 07:42:27 +02:00
  • dbff694e3d cxxrtl: Use the base name of the interface file for the include directive Henri Nurmi 2023-12-09 22:27:05 +02:00
  • 3ea6bca23e Bump version github-actions[bot] 2023-12-13 00:16:10 +00:00
  • f44e8d0124 Working on extensions doc Krystine Sherwin 2023-12-13 11:34:42 +13:00
  • afe8eff790 Merge updated master into krys/docs Krystine Sherwin 2023-12-13 10:17:11 +13:00
  • 7f24ef37f8 Add todo Krystine Sherwin 2023-12-13 10:15:51 +13:00
  • 1733a76273 Updated ABC info Krystine Sherwin 2023-12-13 10:08:45 +13:00
  • 5837fe8c91 Merge pull request #4067 from povik/cxxrtl-udivmod-fix Martin Povišer 2023-12-12 21:22:25 +01:00
  • 320e75a3e3 Merge pull request #4065 from daglem/fix-AST_SHIFT-AST_SHIFTX Martin Povišer 2023-12-12 11:47:29 +01:00
  • 7bded221a7 Merge pull request #4066 from daglem/dump_vlog-more-ast-nodes Martin Povišer 2023-12-12 11:30:07 +01:00
  • 18d1907fa8 cxxrtl: Assert well-formedness of input to udivmod Martin Povišer 2023-12-12 09:52:35 +01:00
  • 6206a3af30 cxxrtl: Handle case of Bits < 4 in formatting of values Martin Povišer 2023-12-12 09:51:17 +01:00
  • e34a25ea27 TODOs Krystine Sherwin 2023-12-12 12:05:45 +13:00
  • c848d98d91 cxxrtl: Fix udivmod logic Martin Povišer 2023-12-11 22:11:35 +01:00
  • bcf5e92389 cxxrtl: Fix ctlz implementation Martin Povišer 2023-12-11 22:10:51 +01:00
  • 655921e851 Uncloak array expressions generated by read_verilog -dump_vlog2 Dag Lem 2023-08-11 23:23:57 +02:00
  • cda470d63e Respect the sign of the right operand of AST_SHIFT and AST_SHIFTX Dag Lem 2023-11-27 15:28:06 +01:00
  • cca12d9d9b Merge pull request #4055 from povik/sim-hier-prints Jannis Harder 2023-12-11 16:55:36 +01:00
  • 2858c33f68 Merge pull request #4058 from povik/fix-py-example N. Engelhardt 2023-12-11 16:49:47 +01:00
  • fe686e725f Merge pull request #4062 from povik/iterator-c++17 Jannis Harder 2023-12-11 16:44:31 +01:00
  • 4ecceaed44 Updates to install and tests Krystine Sherwin 2023-12-11 12:44:05 +13:00
  • 373b651d5b Bump version github-actions[bot] 2023-12-10 00:17:47 +00:00
  • 4cce491639 celledges: s/x_jump/zpad_jump/ Martin Povišer 2023-12-10 00:27:42 +01:00
  • 0681baae19 cxxrtl: Extract divmod algorithm into value Merry 2023-12-09 14:37:53 +00:00
  • 99c8143ded cxxrtl: Remove redundant divmod Merry 2023-12-09 14:07:54 +00:00
  • 80b8cd19c4 rtlil: Fix value type for iterator over SigSpec Martin Povišer 2023-12-09 18:48:30 +01:00
  • 189064b8da rtlil, hashlib: Remove deprecated std::iterator usage Martin Povišer 2023-12-09 18:43:38 +01:00
  • f949579cf3 Testing latexpdf build Krystine Sherwin 2023-12-08 11:19:12 +13:00
  • 25f6a98f52 Updating the intro Krystine Sherwin 2023-12-08 10:46:05 +13:00
  • aef9921fc9 Tidying TODOs Krystine Sherwin 2023-12-08 09:46:02 +13:00