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Mono Color

• e6021b2b48 Merge pull request #4057 from jix/peepopt_shiftmul_right_padding_fix Martin Povišer 2023-12-07 14:56:53 +01:00
• 44c72e5223 python: Fix import in plugin example Martin Povišer 2023-12-07 14:31:56 +01:00
• 1e3b90ae56 Removing typical phases doc Krystine Sherwin 2023-12-07 17:14:21 +13:00
• fb4cbfa735 Bump version github-actions[bot] 2023-12-07 00:16:21 +00:00
• f9ce3d1c26 WIP merging synth phases with example Krystine Sherwin 2023-12-07 13:04:46 +13:00
• 7b74caa5db peepopt: Fix padding for the peepopt_shiftmul_right pattern Jannis Harder 2023-12-06 18:22:19 +01:00
• 6581b5593c sim: Print hierarchy for failed assertions Martin Povišer 2023-12-06 11:59:19 +01:00
• 45dd9eca64 Merge pull request #4051 from YosysHQ/wasi_ci Miodrag Milanović 2023-12-06 10:52:13 +01:00
• 6dc62bd013 Fix out of tree build Miodrag Milanovic 2023-12-06 09:56:35 +01:00
• 56abf92b85 Add WASI CI build Miodrag Milanovic 2023-12-06 09:19:11 +01:00
• d71dd5b9bb Fix out of tree build Miodrag Milanovic 2023-12-06 09:11:51 +01:00
• a530321042 Bump version github-actions[bot] 2023-12-06 00:16:15 +00:00
• 093f9c7bac Merge pull request #4053 from povik/pmgen-make Martin Povišer 2023-12-05 19:56:09 +01:00
• 16ea497d7c pmgen: Have a single make pattern Martin Povišer 2023-12-05 18:29:14 +01:00
• 0ccff57062 Next dev cycle Miodrag Milanovic 2023-12-05 08:58:28 +01:00
• 8f07a0d840 Release version 0.36 yosys-0.36 Miodrag Milanovic 2023-12-05 08:55:12 +01:00
• 2ffea67b04 Bump version github-actions[bot] 2023-12-05 00:16:14 +00:00
• bad8dba2cd Correcting plurals Krystine Sherwin 2023-12-05 11:22:00 +13:00
• a8b2525b08 typical phases: Expand/split sections Krystine Sherwin 2023-12-05 11:21:39 +13:00
• b1bbb5827a Merge pull request #4050 from povik/ql-bram_types-gen Martin Povišer 2023-12-04 20:04:20 +01:00
• e0fc48e196 quicklogic: Generate bram_types_sim.v at build time Martin Povišer 2023-12-04 18:07:08 +01:00
• 8738143880 Merge pull request #4045 from povik/upstream-ql-k6n10f Miodrag Milanović 2023-12-04 16:47:17 +01:00
• 96fecf0716 Revert "Add attributes to module instantiation" Miodrag Milanovic 2023-12-04 16:37:01 +01:00
• 22cc4aff51 quicklogic: Test TDP36K inference with initial data Martin Povišer 2023-12-04 15:47:50 +01:00
• e5c32f399a synth_quicklogic: Testing double_sync_ram_tdp Krystine Sherwin 2023-12-04 11:17:18 +13:00
• 97354782c0 Adding double_sync_ram_tdp to blockram.v Krystine Sherwin 2023-12-04 11:16:50 +13:00
• 215a777eb3 qlf_tests: minor adjustment Krystine Sherwin 2023-12-04 09:24:19 +13:00
• 33ca6994b7 remove example test N. Engelhardt 2023-12-01 14:28:50 +01:00
• 3c5b0ab164 fix test setup for synth_quicklogic memory tests N. Engelhardt 2023-12-01 10:47:39 +01:00
• 509d176523 attempting to sim split memory tests Krystine Sherwin 2023-12-01 21:16:58 +13:00
• 0d1668c1ee QLF_TDP36K: asymmetric simulation tests Krystine Sherwin 2023-12-01 20:47:39 +13:00
• 497cd021af QLF_TDP36K: truncation tests matter Krystine Sherwin 2023-12-01 17:14:01 +13:00
• 7f12d0ba95 QLF_TDP36K: more basic tdp/sdp sim tests Krystine Sherwin 2023-12-01 17:00:15 +13:00
• 3d08ed216d QLF_TDP36K: parameterised sim test gen Krystine Sherwin 2023-12-01 12:55:59 +13:00
• ba3be3fd1c QLF_TDP36K: test bram_tdp post synth Krystine Sherwin 2023-12-01 09:47:46 +13:00
• f9c8978128 add example memory test N. Engelhardt 2023-11-30 19:35:43 +01:00
• ede4eaeee2 quicklogic: wildcard asymmetric memory tests Krystine Sherwin 2023-11-30 12:41:03 +13:00
• 8ded7020f4 tests: asymmetric sync rams now correctly asymmetric Krystine Sherwin 2023-11-30 12:36:21 +13:00
• ba09866217 quicklogic: testing port widths on split rams Krystine Sherwin 2023-11-30 11:41:41 +13:00
• 1a843b2a86 quicklogic: testing 1:4 assymetric memory Krystine Sherwin 2023-11-30 11:17:24 +13:00
• 7513bfcbfe quicklogic: fix double width read Krystine Sherwin 2023-11-30 09:16:12 +13:00
• 8d3b238b9b quicklogic: Testing split TDP36K Krystine Sherwin 2023-11-29 17:34:22 +13:00
• 991850e1c9 quicklogic: Initial blockram tests Krystine Sherwin 2023-11-29 16:48:20 +13:00
• e0a6a01ecb quicklogic: Add RAM_INIT to specialized BRAM models Martin Povišer 2023-11-30 10:41:55 +01:00
• 4903f99f85 quicklogic: Add missing RAM_INIT param on TDP36K sim model Martin Povišer 2023-11-29 11:04:34 +01:00
• b602c0858f quicklogic: Set initial values on inferred TDP36K Martin Povišer 2023-11-27 17:31:46 +01:00
• a5c8d246f7 quicklogic: Add k6n10f DSP test Martin Povišer 2023-11-27 17:18:33 +01:00
• b30544d61d ql_dsp_io_regs: Fix ID strings, constant detection Martin Povišer 2023-11-27 17:17:03 +01:00
• db9e5b4f14 quicklogic: Fix dffs.ys test Martin Povišer 2023-11-27 17:27:35 +01:00
• dad85b5178 synth_quicklogic: Fix missing FF mapping Martin Povišer 2023-11-27 14:22:28 +01:00
• 532aca28ab quicklogic: Drop blackbox off adder_carry Martin Povišer 2023-11-27 14:21:59 +01:00
• 554d8caef7 quicklogic: Add basic k6n10f tests Martin Povišer 2023-11-27 12:14:48 +01:00
• e19833f8c7 synth_quiclogic: Fix conditioning of bram passes Martin Povišer 2023-10-09 13:18:09 +02:00
• 6672b6c1b3 quicklogic: Move pp3 tests one level down Martin Povišer 2023-10-09 13:13:42 +02:00
• e43810e13f ql_dsp_macc: Tune DSP inference code Martin Povišer 2023-10-02 15:55:41 +02:00
• 7d738b07da ql_dsp_*: Clean up Martin Povišer 2023-10-02 14:40:10 +02:00
• 4bb4fd358e ql_k6n10f: Remove support for parameter-configured DSP variety Martin Povišer 2023-09-29 14:31:06 +02:00
• b80b1ab8b6 merge brams_final_map.v into brams_map.v N. Engelhardt 2023-09-18 12:45:06 +02:00
• 20d864bbde add dsp inference N. Engelhardt 2023-11-27 10:35:29 +01:00
• 6682693888 change ql-bram-types pass to use mode parameter; clean up primitive libraries N. Engelhardt 2023-08-14 16:20:36 +02:00
• 48c1fdc33d add qlf_k6n10f architecture + bram inference N. Engelhardt 2023-11-27 09:42:40 +01:00
• 98769010af synth_quicklogic: rearrange files to prepare for adding more architectures N. Engelhardt 2023-07-07 15:27:21 +02:00
• 8bd681acfc Bump version github-actions[bot] 2023-12-04 00:16:38 +00:00
• 7343ef159e synth_quicklogic: Testing double_sync_ram_tdp krys/ql-tests Krystine Sherwin 2023-12-04 11:17:18 +13:00
• 945e78e266 Adding double_sync_ram_tdp to blockram.v Krystine Sherwin 2023-12-04 11:16:50 +13:00
• 2d6738bb10 qlf_tests: minor adjustment Krystine Sherwin 2023-12-04 09:24:19 +13:00
• bf955cc2b0 nexus: Fix format strings to remove space padding gatecat 2023-12-01 10:20:21 +01:00
• f19c6b4415 Enable bram for Gowin Pepijn de Vos 2023-12-03 10:17:28 +01:00
• 1bd3678f75 remove example test N. Engelhardt 2023-12-01 14:28:50 +01:00
• c2fc33f0eb fix test setup for synth_quicklogic memory tests N. Engelhardt 2023-12-01 14:03:07 +01:00
• 190cbd54b1 fix test setup for synth_quicklogic memory tests N. Engelhardt 2023-12-01 10:47:39 +01:00
• 5634d98ccb attempting to sim split memory tests Krystine Sherwin 2023-12-01 21:16:58 +13:00
• d9d54e66c7 QLF_TDP36K: asymmetric simulation tests Krystine Sherwin 2023-12-01 20:47:39 +13:00
• 0cd4a10c81 QLF_TDP36K: truncation tests matter Krystine Sherwin 2023-12-01 17:14:01 +13:00
• 7f90fafd15 QLF_TDP36K: more basic tdp/sdp sim tests Krystine Sherwin 2023-12-01 17:00:15 +13:00
• 7a659bdd26 QLF_TDP36K: parameterised sim test gen Krystine Sherwin 2023-12-01 12:55:59 +13:00
• b62173775c QLF_TDP36K: test bram_tdp post synth Krystine Sherwin 2023-12-01 09:47:46 +13:00
• 64609afe2c add example memory test N. Engelhardt 2023-11-30 19:35:43 +01:00
• f810bd88f5 quicklogic: wildcard asymmetric memory tests Krystine Sherwin 2023-11-30 12:41:03 +13:00
• c54d6b29d3 tests: asymmetric sync rams now correctly asymmetric Krystine Sherwin 2023-11-30 12:36:21 +13:00
• cdb20baf1f quicklogic: testing port widths on split rams Krystine Sherwin 2023-11-30 11:41:41 +13:00
• 4c03c84fa7 quicklogic: testing 1:4 assymetric memory Krystine Sherwin 2023-11-30 11:17:24 +13:00
• a1073c706e quicklogic: fix double width read Krystine Sherwin 2023-11-30 09:16:12 +13:00
• fbf8607b97 quicklogic: Testing split TDP36K Krystine Sherwin 2023-11-29 17:34:22 +13:00
• 0cd67ce473 quicklogic: Initial blockram tests Krystine Sherwin 2023-11-29 16:48:20 +13:00
• fb34167fd4 fixup! quicklogic: Add basic k6n10f tests Martin Povišer 2023-11-30 13:43:56 +01:00
• d11a85fcba fixup! quicklogic: Add basic k6n10f tests Martin Povišer 2023-11-30 11:12:55 +01:00
• 193144e68b fixup! quicklogic: Add basic k6n10f tests Martin Povišer 2023-11-30 10:45:39 +01:00
• 49cee23128 quicklogic: Add RAM_INIT to specialized BRAM models Martin Povišer 2023-11-30 10:41:55 +01:00
• a47c2aaa97 fixup! quicklogic: Add missing RAM_INIT param on TDP36K sim model Martin Povišer 2023-11-30 10:18:48 +01:00
• e70122b74e fixup! quicklogic: Add basic k6n10f tests Martin Povišer 2023-11-29 11:20:16 +01:00
• 6066115d5b quicklogic: Add missing RAM_INIT param on TDP36K sim model Martin Povišer 2023-11-29 11:04:34 +01:00
• 8614d9b32f Bump version github-actions[bot] 2023-11-29 00:16:09 +00:00
• 62bbd086b1 cxxrtl: reorganize runtime component files. Catherine 2023-11-28 12:09:47 +00:00
• 3dd5262355 Add *.dwo files to .gitignore Catherine 2023-11-28 11:31:21 +00:00
• 04d2f55bec fixup! add qlf_k6n10f architecture + bram inference Martin Povišer 2023-11-27 18:28:10 +01:00
• 53bda484f8 quicklogic: Set initial values on inferred TDP36K Martin Povišer 2023-11-27 17:31:46 +01:00
• 5bc587c843 quicklogic: Add k6n10f DSP test Martin Povišer 2023-11-27 17:18:33 +01:00
• 03b45c883a ql_dsp_io_regs: Fix ID strings, constant detection Martin Povišer 2023-11-27 17:17:03 +01:00
• 502559cba4 quicklogic: Fix dffs.ys test Martin Povišer 2023-11-27 17:27:35 +01:00