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Mono Color

• 9a9aa2c45a Finished presentation intro Krystine Sherwin 2023-08-03 09:20:30 +12:00
• 20c2708383 Move presentation intro example Krystine Sherwin 2023-08-03 09:20:29 +12:00
• cd6e63e1a9 Moved presentation_prog Krystine Sherwin 2023-08-03 09:20:29 +12:00
• 045c04096e Reorganising documentation Krystine Sherwin 2023-08-03 09:20:29 +12:00
• 4f1cd66829 New structure headings Krystine Sherwin 2023-08-03 09:20:24 +12:00
• f37ce5c839 Bump version github-actions[bot] 2023-08-02 00:16:17 +00:00
• 77c7355d53 smtbmc: Avoid quadratic behavior when scanning s-exprs Jannis Harder 2023-08-01 17:19:29 +02:00
• b9751ef0b0 Install yw.h and json.h Jannis Harder 2023-07-24 16:40:43 +02:00
• f8325f66b7 opt_expr: Fix 'signed X>=0' replacement for wide output ports Martin Povišer 2023-08-01 11:10:27 +02:00
• 8b2a3d60f4 Merge pull request #3841 from povik/test-aigmap Miodrag Milanović 2023-08-01 09:04:47 +02:00
• 6bf6e3307c Bump version github-actions[bot] 2023-08-01 00:19:43 +00:00
• 93988ef5df tests: Extend aigmap.ys with SAT comparison Martin Povišer 2023-07-10 12:40:50 +02:00
• 0a3f805daa Merge pull request #3840 from povik/cellaigs-cmp-cells Jannis Harder 2023-07-31 16:23:39 +02:00
• 809466c5c5 Merge pull request #3861 from YosysHQ/verific_blackbox Miodrag Milanović 2023-07-31 16:11:16 +02:00
• a43e26e3e9 Merge pull request #3865 from dragonmux/fix/rtlil-teardown-segfault Miodrag Milanović 2023-07-31 16:10:39 +02:00
• 19d5293657 when blackboxing no need to know missing modules Miodrag Milanovic 2023-07-31 09:18:54 +02:00
• ef7e358576 kernel/rtlil: Trailing whitespace cleanup dragonmux 2023-07-26 20:50:55 +01:00
• b59c717245 kernel/rtlil: Fixed the destruction guard for IdString dragonmux 2023-07-26 20:46:56 +01:00
• 3ec00cceaa cellaigs: Generate models for integer comparison cells Martin Povišer 2023-07-10 12:28:22 +02:00
• 372760af57 spaces to tabs Miodrag Milanovic 2023-07-24 16:18:21 +02:00
• 3989181cd6 Add ability to blackbox modules/units from file while reading with verific Miodrag Milanovic 2023-07-24 12:41:57 +02:00
• b04d0e09e8 Merge pull request #3830 from povik/cellaigs-header N. Engelhardt 2023-07-24 16:33:11 +02:00
• 5e8db7000c Merge pull request #3839 from povik/python-log-newline N. Engelhardt 2023-07-24 16:28:02 +02:00
• 43780c9812 Merge pull request #3838 from povik/various-cleanup N. Engelhardt 2023-07-24 16:24:23 +02:00
• 2bc0d86de7 Merge pull request #3854 from povik/abits-wide_log2-assert N. Engelhardt 2023-07-24 16:20:51 +02:00
• c7670b36d4 Bump version github-actions[bot] 2023-07-24 00:17:45 +00:00
• 6965abeefa abc, abc9_exe: fix build on WASI (and others with const* stdout). Catherine 2023-07-23 01:36:37 +00:00
• 411b6e98cd abc, abc9_exe: respect -q when built with linked ABC. Catherine 2023-07-22 21:47:03 +00:00
• c023b9485a Bump version github-actions[bot] 2023-07-22 00:17:24 +00:00
• d5d2bf815a Fix semantic merge conflict in previous two merged PRs Zachary Snow 2023-07-21 00:08:10 -04:00
• 72a4022a10 ast/simplify: Retire 'at_zero' flag Martin Povišer 2023-04-04 22:53:01 +02:00
• 4fceeb3b32 ast/simplify: Use clone_at_zero() for "at_zero" evaluations Martin Povišer 2023-06-21 13:45:42 +02:00
• 77d4b5230e ast: Move to a new helper method to print input errors Martin Povišer 2023-04-04 11:53:50 +02:00
• 1ac1b2eed5 ast/simplify: Factor out helper to determine range width Martin Povišer 2023-04-04 11:34:17 +02:00
• cff53d6d87 Corrected handling of nested typedefs of struct/union Dag Lem 2023-01-29 20:22:00 +01:00
• 0b8f728590 Bump version github-actions[bot] 2023-07-21 00:17:07 +00:00
• f5485b59a9 sim: Bail if there are blackboxes in simulation Martin Povišer 2023-07-19 16:57:49 +02:00
• 51ef942547 verilog_backend: Use hashlib dict for auto_name_map Martin Povišer 2023-07-19 16:56:58 +02:00
• 596743a6b6 verilog_backend: Make the keywords pool static Martin Povišer 2023-07-19 16:55:30 +02:00
• f0ae046c5a opt_share: Fix input confusion with ANDNOT, ORNOT gates Martin Povišer 2023-07-19 20:08:22 +02:00
• 6a553568c5 kernel/mem: Assert ABITS is not below wide_log2 Martin Povišer 2023-07-19 16:48:15 +02:00
• 83c9261d6c Bump version github-actions[bot] 2023-07-19 00:31:56 +00:00
• 4fff228b0c Next dev cycle Miodrag Milanovic 2023-07-18 08:47:52 +02:00
• f3c6b41050 Release version 0.31 yosys-0.31 Miodrag Milanovic 2023-07-18 08:45:00 +02:00
• 25d4b3a5dc Bump version github-actions[bot] 2023-07-18 00:26:17 +00:00
• 2be5c0786f Merge pull request #3826 from nakengelhardt/nak/mem_libmap_print_attr N. Engelhardt 2023-07-17 16:35:10 +02:00
• 5584ce95db log: Detect newlines in Python log output Martin Povišer 2023-07-10 12:40:18 +02:00
• 0d5e9acd34 README.md: s/write_ilang/write_rtlil/ Martin Povišer 2023-07-10 12:54:02 +02:00
• eb083c5d4b extract_counter: Update help and comments after UP/DOWN support Martin Povišer 2023-07-10 12:34:04 +02:00
• 8839d7fa5a cellaigs: Fix the case of $_NMUX_ cells Martin Povišer 2023-07-10 12:27:50 +02:00
• 78d13d1956 Mention 'bwmuxmap' in 'write_firrtl' help Martin Povišer 2023-07-10 12:22:58 +02:00
• c0b1a7daa4 Drop stray 'cellaigs.h' include from backend passes Martin Povišer 2023-07-10 12:21:49 +02:00
• 7c6cc4c40b tests: Fix invocation of 'help -cells' Martin Povišer 2023-07-10 12:20:48 +02:00
• 06256c0c00 Slightly adjust the wording of "write_blif" help Martin Povišer 2023-07-10 12:20:19 +02:00
• 57de249881 memory_libmap: print additional debug messages when no valid mapping is found N. Engelhardt 2023-07-06 18:54:32 +02:00
• 991bff00f1 Makefile: install cellaigs.h header Martin Povišer 2023-07-04 00:50:38 +02:00
• 14d50a176d Merge pull request #3676 from nakengelhardt/dfflegalize_scratchpad_minarg N. Engelhardt 2023-07-03 17:15:21 +02:00
• a6be7b4751 memory_libmap: add debug messages for some reasons for rejecting mappings N. Engelhardt 2023-06-29 14:02:08 +02:00
• b5b0b7e839 Bump version github-actions[bot] 2023-06-29 00:18:55 +00:00
• 7542146fc5 memory_libmap: print message about attributes forcing ram kind N. Engelhardt 2023-06-28 17:48:20 +02:00
• eb397592f0 cxxrtl: add $divfloor. Charlotte 2023-06-28 11:47:30 +10:00
• 911a76affa Merge pull request #3825 from jix/abc-fold-s Jannis Harder 2023-06-28 13:05:30 +02:00
• a7bccdfe8d Update ABC version Jannis Harder 2023-06-28 11:20:44 +02:00
• 596da3f2a6 Merge pull request #3815 from charlottia/py312-syntax Jannis Harder 2023-06-26 16:36:58 +02:00
• 6be5f6449c Merge pull request #3816 from jix/smtbmc-cover-keepgoing Jannis Harder 2023-06-26 16:35:52 +02:00
• b87af9cec0 Merge pull request #3817 from jix/constant_drive_conflict Jannis Harder 2023-06-26 16:19:50 +02:00
• 2310a0ea9a Bump version github-actions[bot] 2023-06-25 00:21:16 +00:00
• 9ba7170919 Merge pull request #3818 from nakengelhardt/nak/verific_import_mem_access_src_loc Miodrag Milanović 2023-06-24 10:42:45 +02:00
• 21686f0d9d verific: import src attribute on $memrd/$memwr cells N. Engelhardt 2023-06-23 19:40:29 +02:00
• a07f8ac38a check: Also check for conflicts with constant drivers Jannis Harder 2023-06-23 18:07:28 +02:00
• f9744fdfcd smtbmc: Make cover mode respect --keep-going Jannis Harder 2023-06-23 10:27:38 +02:00
• 3f29bdbbc5 smt2: py3.12+: avoid SyntaxWarning. Charlotte 2023-06-23 14:38:15 +10:00
• f9257d3192 Merge pull request #3811 from YosysHQ/micko/defaultvalue Miodrag Milanović 2023-06-22 09:39:45 +02:00
• 8f7a9a0b66 Bump version github-actions[bot] 2023-06-22 00:17:44 +00:00
• 51e627686a Merge pull request #3812 from charlottia/iterator-invalidation Claire Xen 2023-06-21 14:46:25 +02:00
• aff0065646 Use defaultvalue for init values of input ports Miodrag Milanovic 2023-06-21 13:21:34 +02:00
• 63e4114233 proc_prune: avoid using invalidated iterator Charlotte 2023-06-21 19:05:02 +10:00
• 941fa70ce1 Merge pull request #3809 from YosysHQ/nak/show_escape N. Engelhardt 2023-06-21 10:38:32 +02:00
• f573aebdd3 Merge pull request #3810 from charlottia/docs-celllib-minor N. Engelhardt 2023-06-21 10:34:59 +02:00
• 0c0171bd60 docs: RD_DATA is an output, not input Charlotte 2023-06-21 17:21:04 +10:00
• 104edb4587 Bump version github-actions[bot] 2023-06-21 00:17:27 +00:00
• 48cafd5ccf Merge pull request #1489 from YosysHQ/clifford/ediflsbidx Claire Xen 2023-06-20 17:58:44 +02:00
• 9c7f0e7670 show: truncate very long module names N. Engelhardt 2023-06-20 12:53:56 +02:00
• 22c9237716 show: escape angle brackets N. Engelhardt 2023-06-20 11:17:12 +02:00
• cff3195caa Improve EDIF lib_cell_ports scan Clifford Wolf 2019-11-14 15:55:21 +01:00
• fb9e12761b Add "write_edif -lsbidx" Clifford Wolf 2019-11-12 17:38:00 +01:00
• 25954715f0 Bump version github-actions[bot] 2023-06-20 00:16:06 +00:00
• d3ee4eba5b Merge pull request #3797 from charlottia/one-length-memories Jannis Harder 2023-06-19 16:21:06 +02:00
• 3fa83ca195 Merge pull request #3808 from YosysHQ/krys/docs N. Engelhardt 2023-06-19 12:12:56 +02:00
• d1b86d2fcf docs: reflow memory map Krystine Sherwin 2023-06-19 12:05:51 +12:00
• c9d31c3c87 smt2: abits needs to be at least 1 for BitVec Charlotte Connor 2023-06-13 14:59:18 +10:00
• 8b2a001021 Bump version github-actions[bot] 2023-06-13 00:17:19 +00:00
• 06f06c7be2 Merge pull request #3801 from jix/witness-aiw2yw-xbits Jannis Harder 2023-06-12 16:12:39 +02:00
• a310bd2d23 Merge pull request #3802 from YosysHQ/micko/build_full Miodrag Milanović 2023-06-12 16:07:06 +02:00
• 8b74e8ad3a Merge pull request #3796 from YosysHQ/micko/update_abc Miodrag Milanović 2023-06-12 16:06:56 +02:00
• 34a6bef768 link verific where appropriate and link full archives Miodrag Milanovic 2023-06-12 10:01:35 +02:00
• 75cf79588e Add ability for user plugin to add new verific log callback Miodrag Milanovic 2023-06-12 10:01:01 +02:00
• dcc4d6e90b yosys-witness: Don't treat aiw x-bits as don't change Jannis Harder 2023-06-09 15:21:22 +02:00
• 236e15f3b0 Merge pull request #3783 from YosysHQ/krys/docs N. Engelhardt 2023-06-09 15:13:42 +02:00
• bac4c55ed6 Merge pull request #3723 from povik/pygen-const Miodrag Milanović 2023-06-09 15:13:23 +02:00