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Mono Color

• e6f7cf3b29 Update tests Miodrag Milanovic 2023-06-09 14:41:45 +02:00
• 5813809ad9 Bump version github-actions[bot] 2023-06-07 00:17:31 +00:00
• 0d4a670267 Update ABC Miodrag Milanovic 2023-06-06 14:37:14 +02:00
• b623888f6a Update ABC to latest Miodrag Milanovic 2023-06-06 11:57:20 +02:00
• c5e4eec3ba Next dev cycle Miodrag Milanovic 2023-06-06 09:41:26 +02:00
• f7a8284c7b Release version 0.30 yosys-0.30 Miodrag Milanovic 2023-06-06 09:38:46 +02:00
• 73badeccef Bump version github-actions[bot] 2023-06-06 00:17:35 +00:00
• 8cb3bab479 Merge pull request #3792 from pu-cc/gatemate-bram-updates Miodrag Milanović 2023-06-05 20:09:03 +02:00
• 61387d78b7 gatemate: Prevent implicit declaration of ram_{we,en} Patrick Urban 2023-06-05 19:08:44 +02:00
• 62fc118548 Merge pull request #3790 from zeldin/makefile-posix-test Miodrag Milanović 2023-06-05 16:21:11 +02:00
• 7c606bd5a3 Merge pull request #3791 from nakengelhardt/nak/show_attr_wires N. Engelhardt 2023-06-05 16:18:54 +02:00
• 6f5d984bdb Merge pull request #3778 from jix/yw_clk2fflogic N. Engelhardt 2023-06-05 16:15:04 +02:00
• 88c849d112 Bump version github-actions[bot] 2023-06-04 00:19:27 +00:00
• d7f25165a5 Add ninitff line to aiger .aim files Claire Xenia Wolf 2023-06-03 14:38:22 +02:00
• 0707b911c7 show: add -viewer none option N. Engelhardt 2023-06-01 10:02:30 +02:00
• 4b986c9c65 fix wire color after BUF N. Engelhardt 2023-05-31 17:38:46 +02:00
• 2004a9ff4a gatemate: Add CC_FIFO_40K simulation model Patrick Urban 2023-05-30 09:06:23 +02:00
• c244a7161b gatemate: Fix SDP read behavior Patrick Urban 2023-05-30 09:05:43 +02:00
• 43b807fe6f Bump version github-actions[bot] 2023-05-30 00:17:12 +00:00
• 1cd1e57e3c Fix use of non-POSIX test expressions in Makefile Marcus Comstedt 2023-05-29 16:53:50 +02:00
• fb7af093a8 intel_alm: re-enable 8x40-bit M10K support Lofty 2023-05-29 05:49:53 +01:00
• 26555a998d show -colorattr: extend colors to arrows when wires have attribute N. Engelhardt 2023-05-24 17:52:14 +02:00
• 8596c5ce49 Bump version github-actions[bot] 2023-05-26 00:15:52 +00:00
• 3aee765793 Initial version of memory mapping doc Krystine Sherwin 2023-04-04 21:31:26 +12:00
• cac1bc6fbe intel_alm: enable M10K initialisation Lofty 2023-05-25 17:48:48 +01:00
• ec8d7b1c68 abc9_ops -prep_hier to unmap entire module Eddie Hung 2023-05-21 18:20:18 -07:00
• 862631d657 Add ABC9 DSP cascade test Eddie Hung 2023-05-21 18:19:51 -07:00
• 00b0e850db intel_alm: re-enable carry chains for ABC9 Lofty 2023-05-25 16:17:09 +01:00
• e36c71b5b7 Use clk2fflogic attr on cells to track original FF names in witnesses Jannis Harder 2023-05-25 12:48:02 +02:00
• 7caeb922a0 sim: Run level triggered async updates to fixpoint during initialization Jannis Harder 2023-05-25 12:46:16 +02:00
• 52c8c28d2c Add recover_names pass to recover names post-mapping gatecat 2021-11-25 19:43:58 +00:00
• 57c9eb70fe Bump version github-actions[bot] 2023-05-24 00:15:32 +00:00
• 5e36effe3c Merge pull request #3777 from YosysHQ/micko/vhdl_verific Miodrag Milanović 2023-05-23 11:44:49 +02:00
• ecd289c100 Fix importing parametrized VHDL entity Miodrag Milanovic 2023-05-23 08:25:08 +02:00
• 4f3d1be96a Merge pull request #3767 from YosysHQ/krys/yw_fix Jannis Harder 2023-05-22 16:10:55 +02:00
• 5fb1223861 Merge pull request #3733 from AdamHillier/aiger-inputs Jannis Harder 2023-05-22 16:09:15 +02:00
• 890849447f Merge pull request #3716 from antmicro/kr/brackets N. Engelhardt 2023-05-22 16:06:38 +02:00
• cdeef5481c Bump version github-actions[bot] 2023-05-22 00:16:53 +00:00
• 18b44a1e84 yosys-witness: add append option to yw2yw Krystine Sherwin 2023-05-22 11:44:19 +12:00
• 8c9a0b51d4 yosys-witness concat yw trace files Krystine Sherwin 2023-05-22 10:13:17 +12:00
• e7156c644d Standard compliance for tests/verilog/block_labels.ys CORRADI Quentin 2023-05-18 14:46:25 +01:00
• ad2b04d63a sim: Fix cosimulation with nested modules having unconnected inputs Jannis Harder 2023-05-18 16:50:11 +02:00
• e6f3914800 smt2: Use smt bv offset for $any*'s smtoffset Jannis Harder 2023-05-18 11:58:09 +02:00
• 147cceb516 Bump version github-actions[bot] 2023-05-18 00:15:34 +00:00
• 52ad7a47f3 Assign wires an smtoffset Krystine Sherwin 2023-05-18 10:37:55 +12:00
• c2285b3460 fix file rights Miodrag Milanovic 2023-05-17 13:39:57 +02:00
• 07e76fcaca Merge pull request #3751 from RTLWorks/main/issue2525 Miodrag Milanović 2023-05-17 13:33:34 +02:00
• 693c609eec Merge branch 'YosysHQ:master' into main/issue2525 Muthiah Annamalai (முத்து அண்ணாமலை) 2023-05-16 21:21:32 -07:00
• 665e0f6131 remove new line per maintainer request Muthu Annamalai 2023-05-17 04:20:13 +00:00
• acfdc5cc42 Merge pull request #3755 from RTLWorks/muthu/issue3498 Miodrag Milanović 2023-05-15 16:34:35 +02:00
• 6b3e6d96a3 Fix missing brackets around else Kamil Rakoczy 2023-03-28 10:53:00 +02:00
• d82bae32be Bump version github-actions[bot] 2023-05-10 00:15:03 +00:00
• c855502bd5 Update passes/techmap/libparse.cc Muthiah Annamalai (முத்து அண்ணாமலை) 2023-05-09 06:40:21 -07:00
• 7aab324e85 Merge pull request #3737 from yrabbit/all-primitives-script Miodrag Milanović 2023-05-09 11:13:51 +02:00
• 5c7cc6ff06 Merge pull request #3745 from rfuest/gowin_alu Miodrag Milanović 2023-05-09 11:12:50 +02:00
• 226a224640 Merge pull request #3749 from lethalbit/aki/plugin-stuff Miodrag Milanović 2023-05-09 08:46:02 +02:00
• f790e00478 Next dev cycle Miodrag Milanovic 2023-05-09 08:00:06 +02:00
• 9c5a60eb20 Release version 0.29 yosys-0.29 Miodrag Milanovic 2023-05-09 07:57:55 +02:00
• 0469405abf Bump version github-actions[bot] 2023-05-09 00:15:34 +00:00
• 266036c6f9 Merge pull request #3756 from YosysHQ/krys/sim_writeback N. Engelhardt 2023-05-08 16:21:24 +02:00
• 0aeb6105eb Merge pull request #3736 from jix/conc_assertion_in_unclocked_proc_ctx N. Engelhardt 2023-05-08 16:15:13 +02:00
• ec56e625f4 Merge pull request #3742 from jix/fix_rename_witness_cell_renames N. Engelhardt 2023-05-08 16:13:28 +02:00
• 5a4e72f57a Fix sim writeback check for yw_cosim Krystine Sherwin 2023-05-08 13:13:09 +12:00
• 17cfc969dd [YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style function body parsing with unittest Muthu Annamalai 2023-05-07 06:19:02 +00:00
• 8341fd450e Merge branch 'master' into all-primitives-script YRabbit 2023-05-07 05:58:35 +10:00
• 4251d37f4f Merge pull request #3610 from YosysHQ/synthprop Miodrag Milanović 2023-05-05 11:03:09 +02:00
• d2f3251528 adding unittest Muthu Annamalai 2023-05-04 22:43:04 -07:00
• 81e089cb60 [YOSYS-2525] fix read_liberty newline handling #2525 - newlines can be allowed in function parsing Muthu Annamalai 2023-05-04 22:30:27 -07:00
• 4f6a66e257 Merge branch 'master' into all-primitives-script YRabbit 2023-05-05 10:21:50 +10:00
• f93671eb85 Bump version github-actions[bot] 2023-05-05 00:15:06 +00:00
• 32f5fca2aa Merge pull request #3694 from daglem/struct-attributes Jannis Harder 2023-05-04 22:15:10 +02:00
• 0b1f45097a Sort cells topologically by default claire/toposort Claire Xenia Wolf 2023-02-09 22:35:03 +01:00
• fb7f3bb290 Cleaner tests for RTLIL cells in struct_dynamic_range.sv Dag Lem 2023-05-04 13:36:57 +02:00
• ad437c178d Handling of attributes for struct / union variables Dag Lem 2023-03-02 19:02:30 +01:00
• bb240665b7 plugin: shuffled the #ifdef WITH_PYTHON's around to un-tangle the code and pulled out the check for the .py extension so it will complain if you try to load a python extension without python support Aki Van Ness 2023-05-03 02:50:23 -04:00
• 572c8df9a8 plugin: Re-vamped how plugin lookup was done to make it more consistent with the rest of yosys, and prevented a case where you could end up with .so.so on the end Aki Van Ness 2023-05-03 02:22:46 -04:00
• 30f1d10948 gowin: Fix X output of $alu techmap Ralf Fuest 2023-05-01 17:56:41 +02:00
• 2bab787729 Merge branch 'master' into all-primitives-script YRabbit 2023-04-26 13:05:20 +10:00
• 7bff8b63b3 rename: Fix renaming cells in -witness mode Jannis Harder 2023-04-25 12:39:00 +02:00
• cee3cb31b9 Merge pull request #3734 from jix/fix_unbased_unsized_const Jannis Harder 2023-04-24 16:08:48 +02:00
• 51dd029024 Bump version github-actions[bot] 2023-04-23 00:17:11 +00:00
• 8611429237 ABC9: Cell Port Bug Patch (#3670) Benjamin Barzen 2023-04-23 01:24:36 +02:00
• a1dd794ff8 gowin: Add all the primitives. YRabbit 2023-04-22 17:10:53 +10:00
• 3cbca5064c verific: Handle non-seq properties with VerificClocking conditions Jannis Harder 2023-04-21 17:19:42 +02:00
• ec47bf1745 verific: Handle conditions when using sva_at_only in VerificClocking Jannis Harder 2023-04-21 16:51:42 +02:00
• 985f4926b7 verilog: Fix const eval of unbased unsized constants Jannis Harder 2023-04-20 12:12:50 +02:00
• 3861cc31f0 Add outputs before inputs to the sigmap in the AIGER backend. AdamHillier 2023-04-19 11:00:51 +00:00
• 7efc50367e Bump version github-actions[bot] 2023-04-19 00:16:35 +00:00
• 88ae463ffe Merge pull request #3732 from hzeller/20230417-remote-statement-no-effect Jannis Harder 2023-04-18 10:45:14 +02:00
• a3a8f7be38 Remove a statement without effect. Henner Zeller 2023-04-17 10:51:10 -07:00
• a9c792dcee Bump version github-actions[bot] 2023-04-15 00:16:41 +00:00
• d0855576ae Next dev cycle Miodrag Milanovic 2023-04-14 09:54:46 +02:00
• 0d6f4b0683 Release version 0.28 yosys-0.28 Miodrag Milanovic 2023-04-14 09:52:15 +02:00
• b377a39b73 Merge pull request #3727 from YosysHQ/micko/pll_bram Miodrag Milanović 2023-04-14 09:34:30 +02:00
• a2655a4b70 Bump version github-actions[bot] 2023-04-13 00:14:37 +00:00
• e56dad56c4 fabulous: Add support for LUT6s gatecat 2023-04-12 13:53:42 +02:00
• f9a6c0fcbd gowin: Add serialization/deserialization primitives YRabbit 2023-04-04 09:41:10 +10:00
• ee3162c58d Add PLL and EBR related primitives Miodrag Milanovic 2023-04-10 12:39:09 +02:00
• 101075611f Bump version github-actions[bot] 2023-04-07 00:14:38 +00:00
• 266f81816b ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model gatecat 2023-04-06 09:29:08 +02:00