read_verilog << EOT

module test();
  wire [31:0] in;
  wire [31:0] out;
  assign out = in + 16;
endmodule

EOT

constmap -cell const_cell O value
select -assert-count 1 t:const_cell
select -assert-count 1 r:value=16

design -reset
read_verilog << EOT

module test();
  wire [31:0] in;
  wire [31:0] out1;
  wire [31:0] out2;
  assign out1 = in + 16;
  assign out2 = in + 32;
endmodule

EOT

constmap -cell const_cell O value
select -assert-count 2 t:const_cell
select -assert-count 1 r:value=16
select -assert-count 1 r:value=32