Emil J. Tywoniak 3a5c492e32 clk2fflogic: fully cover $dffsr tests

2026-01-21 14:48:32 +01:00

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.gitignore

Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.

2025-07-22 10:38:38 +00:00

alu.v

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asserts_seq.v

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asserts_seq.ys

tests: Run async2sync before sat and/or sim to handle $check cells

2024-02-01 16:14:11 +01:00

asserts.v

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asserts.ys

tests: Run async2sync before sat and/or sim to handle $check cells

2024-02-01 16:14:11 +01:00

bug2595.ys

Remove references to ilang

2024-11-05 12:36:31 +13:00

clk2fflogic.ys

clk2fflogic: fully cover $dffsr tests

2026-01-21 14:48:32 +01:00

counters-repeat.v

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counters-repeat.ys

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counters.v

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counters.ys

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dff.ys

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expose_dff.v

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expose_dff.ys

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fminit_noexpand.ys

fix(parse): #5234 adjust width of rhs according to lhs

2025-09-16 15:24:23 +02:00

fminit_seq_width.ys

fix(parse): #5234 adjust width of rhs according to lhs

2025-09-16 15:24:23 +02:00

grom_computer.v

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grom_cpu.v

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grom.ys

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initval.v

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initval.ys

tests: Run async2sync before sat and/or sim to handle $check cells

2024-02-01 16:14:11 +01:00

ram_memory.v

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run-test.sh

test: restore verific handling, nicer naming

2024-12-13 10:24:47 +01:00

share.v

share: Cleanup and additional testing

2025-04-15 12:34:46 +02:00

share.ys

share: Cleanup and additional testing

2025-04-15 12:34:46 +02:00

sim_counter.ys

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sizebits.sv

Add support for $dimensions and $unpacked_dimensions

2024-02-11 11:26:52 -05:00

sizebits.ys

tests: Run async2sync before sat and/or sim to handle $check cells

2024-02-01 16:14:11 +01:00

splice.v

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splice.ys

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