dbc38d72cf
Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
7 lines
127 B
Verilog
7 lines
127 B
Verilog
module test(a, b, c, d, x, y);
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input [15:0] a, b, c, d;
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input [31:0] x;
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output [31:0] y;
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assign y = a*b + (c*d + x);
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endmodule
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