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YosysHQ.yosys
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techlibs
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quicklogic
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pp3
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N. Engelhardt
98769010af
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
..
abc9_map.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
abc9_model.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
abc9_unmap.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
cells_map.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
cells_sim.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
ffs_map.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
latches_map.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
lut_map.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
