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YosysHQ.yosys/tests/fmt
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Miodrag Milanovic 76732497b9 Cleanup
2026-04-16 11:00:44 +02:00
..
fuzz
fmt: merge fuzzers since we don't rely on BigInteger logic
2023-08-11 04:46:52 +02:00
.gitignore
Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.
2025-07-22 10:38:38 +00:00
always_comb_tb.cc
cxxrtl: include iostream when prints are used
2023-08-17 07:08:22 +02:00
always_comb_tb.v
cxxrtl: store comb $print cell last EN/ARGS in module
2023-08-11 04:46:52 +02:00
always_comb.v
cxxrtl: WIP: adjust comb display cells to only fire on change
2023-08-11 04:46:52 +02:00
always_display.v
fmt: add tests for Verilog round trip of format expressions.
2023-08-11 04:46:52 +02:00
always_full_tb.cc
cxxrtl: always lazily format print messages.
2024-01-19 18:55:23 +00:00
always_full_tb.v
verilog_backend: emit sync $print cells with same triggers together
2023-08-11 04:46:52 +02:00
always_full.v
verilog_backend: emit sync $print cells with same triggers together
2023-08-11 04:46:52 +02:00
display_lm_tb.cc
cxxrtl: include iostream when prints are used
2023-08-17 07:08:22 +02:00
display_lm.v
fmt: rudimentary %m support (= %l)
2023-08-11 04:46:52 +02:00
generate_mk.py
Cleanup
2026-04-16 11:00:44 +02:00
initial_display.v
fmt: format %t consistently at initial
2023-08-11 04:46:52 +02:00
roundtrip_tb.v
fmt: add tests for Verilog round trip of format expressions.
2023-08-11 04:46:52 +02:00
roundtrip.v
fmt: add tests for Verilog round trip of format expressions.
2023-08-11 04:46:52 +02:00