12 lines
166 B
Verilog
12 lines
166 B
Verilog
module dlatchsr( input d, set, clr, en, output reg q );
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always @* begin
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if ( clr )
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q = 0;
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else if (set)
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q = 1;
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else
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if (en)
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q = d;
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end
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endmodule
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