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YosysHQ.yosys/tests/sim/sim_dffe.ys
Miodrag Milanovic 271ac28b41 Added test cases
2022-02-16 13:27:59 +01:00

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read_verilog dffe.v
proc
opt_dff
stat
select -assert-count 1 t:$dffe
sim -clock clk -r tb_dffe.fst -scope tb_dffe.uut -sim-cmp dffe