1eb5181700
`read_verilog` supports checking both the current directory and the source directory for relative includes. Make sure we aren't regressing that.
5 lines
89 B
Verilog
5 lines
89 B
Verilog
`include "temp_foo.v"
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module top (input x, output y);
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foo bar (.a(x), .b(y));
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endmodule
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