11 lines
182 B
Systemverilog
11 lines
182 B
Systemverilog
module foo #(parameter [1:0] a) (output [1:0] o);
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assign o = a;
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endmodule
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module top(output [1:0] o);
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foo #(2'b0x) foo(o);
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always_comb begin
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assert(o == 2'b00);
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end
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endmodule
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