Clifford Wolf 001c9f1d45 Fix Verific handling of single-bit anyseq/anyconst wires ...

Signed-off-by: Clifford Wolf <clifford@clifford.at>

2018-05-25 15:41:45 +02:00

..

ast

Replace -ignore_redef with -[no]overwrite

2018-05-03 15:25:59 +02:00

blif

Increase maximum LUT size in blifparse to 12 bits

2017-09-27 15:27:42 +02:00

ilang

Added avail params to ilang format, check module params in 'hierarchy -check'

2016-10-22 11:05:49 +02:00

json

Parse reals as string in JSON front-end

2017-09-26 14:37:03 +02:00

liberty

Also interpret '&' in liberty functions

2018-05-12 20:55:31 +02:00

verific

Fix Verific handling of single-bit anyseq/anyconst wires

2018-05-25 15:41:45 +02:00

verilog

Support SystemVerilog `` extension for macros

2018-05-17 00:09:56 -04:00