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YosysHQ.yosys/tests/functional/single_cells/rtlil
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Roland Coeurjoly 80582ed3af Check the existance of a different set of outputs. No need for (push 1) nor (pop 1)
2024-08-21 11:02:31 +01:00
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ff.il
Added $ff test
2024-08-21 11:02:31 +01:00
multiple_outputs.il
Check the existance of a different set of outputs. No need for (push 1) nor (pop 1)
2024-08-21 11:02:31 +01:00
README.md
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test_cell_add_00000.il
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test_cell_alu_00000.il
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test_cell_and_00000.il
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test_cell_bmux_00000.il
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test_cell_demux_00000.il
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test_cell_div_00000.il
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test_cell_divfloor_00000.il
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test_cell_eq_00000.il
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test_cell_fa_00000.il
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test_cell_ge_00000.il
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test_cell_gt_00000.il
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test_cell_lcu_00000.il
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test_cell_le_00000.il
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test_cell_logic_and_00000.il
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test_cell_logic_not_00000.il
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test_cell_logic_or_00000.il
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test_cell_lt_00000.il
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test_cell_lut_00000.il
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test_cell_macc_00000.il
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test_cell_mod_00000.il
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test_cell_modfloor_00000.il
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test_cell_mul_00000.il
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test_cell_mux_00000.il
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test_cell_ne_00000.il
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test_cell_neg_00000.il
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test_cell_not_00000.il
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test_cell_or_00000.il
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test_cell_pos_00000.il
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test_cell_pos_00001.il
Fix corner case of pos cell with input and output being same width
2024-08-21 11:02:31 +01:00
test_cell_reduce_and_00000.il
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test_cell_reduce_bool_00000.il
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test_cell_reduce_or_00000.il
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test_cell_reduce_xnor_00000.il
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test_cell_reduce_xor_00000.il
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test_cell_shift_00000.il
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test_cell_shiftx_00000.il
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test_cell_shl_00000.il
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test_cell_shr_00000.il
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test_cell_sop_00000.il
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test_cell_sshl_00000.il
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test_cell_sshr_00000.il
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test_cell_sub_00000.il
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test_cell_xnor_00000.il
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test_cell_xor_00000.il
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README.md

Creation of test files

yosys -p "test_cell -n 1 -w test_cell all"

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