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00a877e09b4c6cf1130e4c0a416af2d5362815b3
YosysHQ.yosys
/
frontends
/
verilog
History
Clifford Wolf
161565be10
Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
2013-03-31 11:19:11 +02:00
..
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00
const2ast.cc
initial import
2013-01-05 11:13:26 +01:00
lexer.l
Improvements and bugfixes for generate blocks with local signals
2013-03-26 11:31:34 +01:00
Makefile.inc
initial import
2013-01-05 11:13:26 +01:00
parser.y
Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
2013-03-31 11:19:11 +02:00
preproc.cc
initial import
2013-01-05 11:13:26 +01:00
verilog_frontend.cc
Implemented proper handling of stub placeholder modules
2013-03-28 09:20:10 +01:00
verilog_frontend.h
initial import
2013-01-05 11:13:26 +01:00