Commit c8e0ac0 introduces a regression on handling case exprs that look
like sva labels. After some debugging, we shouldn't push the identifier
ast node to the ast_stack, otherwise, we will get the following
assertion failure:
```
➜ /tmp yosys -p 'read -sv a1.v'
/----------------------------------------------------------------------------\
| yosys -- Yosys Open SYnthesis Suite |
| Copyright (C) 2012 - 2025 Claire Xenia Wolf <claire@yosyshq.com> |
| Distributed under an ISC-like license, type "license" to see terms |
\----------------------------------------------------------------------------/
Yosys 0.57+1 (git sha1 baa61a146, clang++ 20.1.8 -fPIC -O3)
-- Running command `read -sv a1.v' --
1. Executing Verilog-2005 frontend: a1.v
Parsing SystemVerilog input from `a1.v' to AST representation.
ERROR: Assert `extra->ast_stack.size() == 1' failed in frontends/verilog/verilog_parser.y:709.
➜ /tmp cat a1.v
module test(input wire A);
localparam TEST = 1;
always_comb begin
case (A)
TEST: assert(1);
endcase
end
endmodule
```
We encountered this issue before but with a different error message[^1],
[^1]: https://github.com/YosysHQ/yosys/issues/862
c30fd46ea3