Although the current style is allowed by the standard, Icarus verilog
doesn't parse default assignments using an implicit net type:
techlibs/ice40/cells_sim.v:305: syntax error
techlibs/ice40/cells_sim.v:1: Errors in port declarations.
Fix this by making sure that ports with default assignments first on
their line.
Fixes: 46d3f03d2 ("Add default assignments to other SB_* simulation models")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
8c05f14b58