Eddie Hung 627a62a797 Make doc consistent

2019-06-14 10:32:46 -07:00

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.gitignore

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adff2dff.v

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cellhelp.py

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cells.lib

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cmp2lut.v

cmp2lut: new techmap pass.

2019-01-02 07:53:31 +00:00

dff2ff.v

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gate2lut.v

gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

2018-12-05 17:13:27 +00:00

Makefile.inc

cmp2lut: new techmap pass.

2019-01-02 07:53:31 +00:00

pmux2mux.v

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prep.cc

Add "wreduce -keepdc", fixes #1016

2019-05-20 15:36:13 +02:00

simcells.v

Fix typo.

2018-12-05 17:13:27 +00:00

simlib.v

Improve $specrule interface

2019-04-23 22:57:10 +02:00

synth.cc

Make doc consistent

2019-06-14 10:32:46 -07:00

techmap.v

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