github.com/YosysHQ.yosys
1
0
Fork 0
mirror of synced 2026-01-26 12:13:24 +00:00
Code Issues Releases Wiki Activity
Files
02df0198b65a2514d1343eeff8827f4e2cf858d0
YosysHQ.yosys/techlibs/xilinx
History
Eddie Hung ca4f8c9444 xilinx: gate specify/attributes from iverilog
2020-05-14 10:33:57 -07:00
..
tests
xilinx: Add simulation model for DSP48 (Virtex 4).
2020-01-29 01:40:00 +01:00
.gitignore
…
abc9_model.v
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
2020-05-14 10:33:56 -07:00
arith_map.v
xilinx: Initial support for LUT4 devices.
2020-02-07 09:03:22 +01:00
brams_init.py
synth_xilinx: Initial Spartan 6 block RAM inference support.
2019-07-11 14:45:48 +02:00
cells_map.v
xilinx: Improve flip-flop handling.
2019-12-18 13:43:43 +01:00
cells_sim.v
xilinx: gate specify/attributes from iverilog
2020-05-14 10:33:57 -07:00
cells_xtra.py
xilinx: Mark IOBUFDS.IOB as external pad
2020-03-20 14:37:38 +01:00
cells_xtra.v
xilinx: Mark IOBUFDS.IOB as external pad
2020-03-20 14:37:38 +01:00
lut4_lutrams.txt
xilinx: Add support for LUT RAM on LUT4-based devices.
2020-02-07 09:03:22 +01:00
lut6_lutrams.txt
xilinx: Add support for LUT RAM on LUT4-based devices.
2020-02-07 09:03:22 +01:00
lut_map.v
xilinx: Initial support for LUT4 devices.
2020-02-07 09:03:22 +01:00
lutrams_map.v
Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram
2019-12-16 12:06:47 -08:00
Makefile.inc
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
2020-05-14 10:33:56 -07:00
mux_map.v
Change synth_xilinx's -nomux to -minmuxf <int>
2019-06-24 10:04:01 -07:00
synth_xilinx.cc
xilinx/ice40/ecp5: zinit requires selected wires, so select them all
2020-05-14 10:33:56 -07:00
xc2v_brams_map.v
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc2v_brams.txt
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc3s_mult_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc3sa_brams.txt
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc3sda_brams.txt
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc3sda_dsp_map.v
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
xc4v_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc5v_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc6s_brams_map.v
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc6s_brams.txt
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc6s_dsp_map.v
xilinx_dsp: Initial DSP48A/DSP48A1 support.
2019-12-22 20:51:14 +01:00
xc6s_ff_map.v
xilinx: Improve flip-flop handling.
2019-12-18 13:43:43 +01:00
xc7_brams_map.v
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc7_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xc7_ff_map.v
xilinx: Improve flip-flop handling.
2019-12-18 13:43:43 +01:00
xc7_xcu_brams.txt
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xcu_brams_map.v
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xcu_dsp_map.v
xilinx: Support multiplier mapping for all families.
2019-10-22 18:06:57 +02:00
xcup_urams_map.v
xilinx: Add URAM288 mapping for xcup
2019-10-23 11:47:44 +01:00
xcup_urams.txt
xilinx: Add URAM288 mapping for xcup
2019-10-23 11:47:44 +01:00
xilinx_dffopt.cc
xilinx: improve xilinx_dffopt message
2020-04-22 16:25:23 -07:00