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YosysHQ.yosys/tests
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Miodrag Milanović e8ce9442a6 Merge pull request #3452 from ALGCDG/master 
Add BLIF names command input plane size check
2022-10-10 16:29:27 +02:00
..
aiger
switch argument order to work with macOS getopt
2020-09-23 12:48:26 +02:00
arch
support file locations containing spaces
2022-08-08 20:30:50 +02:00
asicworld
…
bind
Add support for parsing the SystemVerilog 'bind' construct
2021-07-16 09:31:39 -04:00
blif
Adding check for BLIF names command input plane size.
2022-08-21 23:18:20 -05:00
bram
Fix the tests we just broke
2021-12-10 00:22:37 +01:00
errors
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fsm
tests: fsm to use a randomly-generated seed
2020-04-24 14:31:33 -07:00
hana
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liberty
dfflibmap: Refactor to use dfflegalize internally.
2020-07-09 18:51:03 +02:00
lut
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memfile
Added 'set -e' into tests/memfile/run-test.sh
2020-02-06 10:45:40 -03:00
memlib
Add memory_libmap tests.
2022-05-18 17:32:56 +02:00
memories
Fix the tests we just broke
2021-12-10 00:22:37 +01:00
opt
Add memory_bmux2rom pass.
2022-05-18 22:48:55 +02:00
opt_share
tests: Parallelize
2020-09-21 15:07:02 +02:00
proc
proc_rom: Add special handling of const-0 address bits.
2022-05-18 17:32:30 +02:00
realmath
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rpc
rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors
2020-03-06 15:29:01 +01:00
sat
Proper example code
2022-03-14 15:39:11 +01:00
select
Merge pull request #1949 from YosysHQ/eddie/select_blackbox
2020-04-22 15:35:05 -07:00
share
…
sim
test dlatchsr and adlatch
2022-02-16 13:58:51 +01:00
simple
Test fixes for latest iverilog
2022-09-21 15:46:43 +02:00
simple_abc9
abc9: fix SCC issues (#2694)
2021-03-29 22:01:57 -07:00
smv
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sva
verific: Use new value change logic also for $stable of wide signals.
2022-05-11 13:05:27 +02:00
svinterfaces
Add a test for interfaces on modules loaded on-demand
2021-07-14 22:54:50 -04:00
svtypes
sv: improve support for wire and var with user-defined types
2021-08-12 22:41:41 -06:00
techmap
opt_mem: Remove constant-value bit lanes.
2022-05-07 23:13:16 +02:00
tools
support file locations containing spaces
2022-08-08 20:30:50 +02:00
unit
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various
Add test for bug 3462
2022-08-29 10:10:09 +02:00
verilog
verilog: fix width/sign detection for functions
2022-05-30 16:45:39 -04:00
vloghtb
Use HTTPS for website links, gatecat email
2021-06-09 12:16:56 +02:00
gen-tests-makefile.sh
support file locations containing spaces
2022-08-08 20:30:50 +02:00